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DATA SHEET
PD784927, 784928, 784927Y, 784928Y
16-BIT SINGLE-CHIP MICROCONTROLLER
MOS INTEGRATED CIRCUIT
DESCRIPTION
The PD784927 and 784928 are members of the NEC 78K/IV Series of microcontrollers equipped with a highspeed, high-performance 16-bit CPU for VCR software servo control. The PD784927Y and 784928Y are based on the PD784928 with the addition of an I2C bus interface compatible with multi-master. They contain many peripheral hardware units ideal for VCR control, such as a multi-function timer unit (super timer unit) for software servo control and VCR analog circuits. Flash memory models, the PD78F4928 and PD78F4928Y, are under development. The functions of the PD784927 is described in detail in the following User's Manual. Be sure to read this manual before designing your system.
PD784928, 784928Y Subseries User's Manual - Hardware
78K/IV Series User's Manual - Instruction
: U12648E : U10905E
FEATURES
* *
High instruction execution speed realized by 16-bit CPU core * Minimum instruction execution time: 250 ns (with 8 MHz internal clock) High internal memory capacity
Item Part Number
PD784927, 784927Y
96K bytes 2048 bytes
PD784928, 784928Y
128K bytes 3584 bytes
Internal ROM capacity Internal RAM capacity
*
VCR analog circuits conforming to VHS Standard * CTL amplifier * RECCTL driver (rewritable) * CFG amplifier * DFG amplifier * DPG amplifier * Reel FG comparator (2 channels) * CSYNC comparator
* DPFG separation circuit (ternary separation circuit)
* * * * * * * * *
Timer unit (super timer unit) for servo control Serial interface : 3 channels 3-wire serial I/O : 2 channels I2C bus interface: 1 channel A/D converter: 12 channels (conversion time: 10 s) Low-frequency oscillation mode: main system clock frequency = internal clock frequency Low-power consumption mode: CPU can operate with a subsystem clock. Supply voltage range: VDD = +2.7 to 5.5 V Hardware watch function: watch operation at low voltage (VDD = 2.7 V (MIN.)) and low current consumption
Unless otherwise specified, the PD784927 is treated as the representative model throughout this document.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U12255EJ2V0DS00 (2nd edition) Date Published December 1999 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1997,1999
PD784927, 784928, 784927Y, 784928Y
APPLICATION FIELDS
Stationary VCR, video camera, In-TV VCR
ORDERING INFORMATION
(1) PD784928 subseries Part Number Package 100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm)
PD784927GC-xxx-8EUNote PD784927GF-xxx-3BA PD784928GC-xxx-8EUNote PD784928GF-xxx-3BA
(2) PD784928Y subseries Part Number
Package 100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm) 100-pin plastic LQFP (fine pitch) (14 x 14 mm) 100-pin plastic QFP (14 x 20 mm)
PD784927YGC-xxx-8EUNote PD784927YGF-xxx-3BA PD784928YGC-xxx-8EUNote PD784928YGF-xxx-3BA
Note Under development
Remark xxx indicates ROM code suffix.
PRODUCT DEVELOPMENT OF VCR-SERVO MICROCONTROLLERS
The product development of VCR-servo microcontrollers is shown below. Enclosed in a frame are subseries names. The Y subseries is a collection of products supporting the I2C bus.
Products under mass production
Products under development
78K/IV series
PD784928
PD784928Y
100-pin QFP. With flash memory. Expanded internal memory capacity. More powerful analog amplifier. Improved VCR functions. Increased I/O. High-current port added. I2C function added (Y model only). 100-pin QFP. Expanded internal memory capacity. Internal analog amplifier. Reinforced super timer. Low-power consumption mode added. 100-pin QFP Expanded internal RAM capacity. Operational amplifier, watch function, multiplier added.
PD784915
78K/I series
PD78148
PD78138
80-pin QFP
2
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
FUNCTION LIST (1/2)
Part Number Item Internal ROM capacity Internal RAM capacity Operating clock 96K bytes 2048 bytes 128K bytes 3584 bytes
PD784927, 784927Y
PD784928, 784928Y
16 MHz (internal clock: 8 MHz) Low frequency oscillation mode : 8 MHz (internal clock: 8 MHz) Low power consumption mode : 32.768 kHz (subsystem clock) 250 ns (with 8 MHz internal clock)
Minimum instruction e x e c u tion time I/O port
74
input : 20 I/O : 54 (including 8 ports for LED direct drive)
Real-time output port Timer/counter
11 (including one each for pseudo VSYNC, head amplifier switch, and chrominance rotation) Timer/counter TM0 (16 bits) TM1 (16 bits) FRC (22 bits) TM3 (16 bits) UDC (5 bits) EC (8 bits) EDV (8 bits) Input signal CFG DFG HSW VSYNC CTL TREEL SREEL * * * * Compare register 3 3 -- 2 1 4 1 Number of bits 22 22 16 22 16 22 22 Capture register -- 1 6 1 -- -- -- Measurable cycle 125 ns to 524 ms 125 ns to 524 ms 1 s to 65.5 ms 125 ns to 524 ms 1 s to 65.5 ms 125 ns to 524 ms 125 ns to 524 ms Remark
For HSW signal generation For CFG signal division Operating edge
Capture register
Super timer unit
VCR special circuit
VSYNC separation circuit, HSYNC separation circuit VISS detection, wide aspect detection circuits Field identification circuit Head amplifier switch/chrominance rotation output circuit Timer TM2 (16 bits) TM4 (16 bits) TM5 (16 bits) Compare register 1 1 (capture/compare) 1 Capture register -- 1 --
General-purpose timer
PWM output
* *
16-bit resolution : 3 channels (carrier frequency: 62.5 kHz) 8-bit resolution : 3 channels (carrier frequency: 62.5 kHz)
Serial interface
3-wire serial I/O: 2 channels (BUSY/STRB control: 1 channel) * I2C bus interface: 1 channel (PD784928Y subseries only) 8-bit resolution x 12 channels, conversion time: 10 s
A/D converter
Data Sheet U12255EJ2V0DS00
3
PD784927, 784928, 784927Y, 784928Y
FUNCTION LIST (2/2)
Part Number Item Analog circuit * * * * * * CTL amplifier RECCTL driver (rewritable) DFG amplifier, DPG amplifier, CFG amplifier DPFG separation circuit (ternary separation circuit) Reel FG comparator (2 channels) CSYNC comparator
PD784927, 784927Y
PD784928, 784928Y
Interrupt sources External Internal Standby function
4 levels (programmable), vectored interrupt, macro service, context switching 9 (including NMI) 22 (including software interrupt) 23 (including software interrupt)
HALT mode/STOP mode/low power consumption mode/low power consumption HALT mode STOP mode can be released by input of valid edge of NMI pin, watch interrupt (INTW), or INTP1/ INTP2/KEY0-KEY4 pins
Watch function Buzzer output function
0.5-second measurement, low-voltage operation (VDD = 2.7 V) 1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (Internal clock: 8 MHz) 2.048 kHz, 4.096 kHz, 32.768 kHz (Subsystem clock: 32.768 kHz)
Supply voltage Package
VDD = +2.7 to 5.5 V * 100-pin plastic LQFP (fine pitch)(14 x 14 mm)Note * 100-pin plastic QFP (14 x 20 mm)
Note
Under development
4
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
PIN CONFIGURATION (Top View)
* 100-pin plastic LQFP (fine pitch)(14 x 14 mm)
PD784927GC-xxx-8EUNote 1, 784928GC-xxx-8EUNote 1 PD784928YGC-xxx-8EU, 784928YGC-xxx-8EUNote 1
P85/PWM3/SCLNote 2 P86/PTO10 P87/PTO11 P30/PTO00 P31/PTO01 P32/PTO02 IC RESET X1 X2 VSS XT2 XT1 VDD P33/SI2/BUSY P34/SO2 P35/SCK2 P36/PWM1 P37/PWM0 P63/SI1 P62/SO1 P61/SCK1/BUZ P60/STRB/CLO P67/PWM5/CTLMON P66/PWM4/CFGMON
P84/PWM2/SDANote 2 P83/ROTC P82/HASW P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07 P06 P05
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 9 67 10 66 11 65 12 64 13 63 14 62 15 61 16 60 17 59 18 58 19 57 20 56 21 55 22 54 23 53 24 52 25 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P65/HWIN/DPGMON P64/BUZ/DFGMON P103/CSYNCIN P102/REEL0IN/INTP3 P101/REEL1IN DFGIN P100/DPGIN CFGCPIN CFGAMP0 CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECCTL- RECCTL+ CTLDLY AVSS2 P113/ANI11 P112/ANI10 P111/ANI9 P110/ANI8 P77/ANI7
Notes 1. Under development 2. Pins SCL and SDA are provided for the PD784928Y subseries only. Caution Directly connect the IC (Internally Connected) pins to VSS in the normal operation mode.
P04 P03 P02 P01 P00 P23/INTP2 P22/INTP1 P21/INTP0 P20/NMI P90/ENV P91/KEY0 P92/KEY1 P93/KEY2 P94/KEY3 P95/KEY4 P96 AVDD2 AVREF P70/ANI0 P71/ANI1 P72/ANI2 P73/ANI3 P74/ANI4 P75/ANI5 P76/ANI6
Data Sheet U12255EJ2V0DS00
5
PD784927, 784928, 784927Y, 784928Y
* 100-pin plastic QFP (14 x 20 mm)
PD784927GF-xxx-3BA, 784928GF-xxx-3BA, PD784927YGF-xxx-3BA, 784928YGF-xxx-3BA
DFGMON/P64/BUZ DPGMON/P65/HWIN CFGMON/P66/PWM4 CTLMON/P67/PWM5 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 P37/PWM0 P36/PWM1 P35/SCK2 P34/SO2 P33/SI2/BUSY VDD XT1 XT2 VSS X2 X1 RESET IC P32/PTO02 P31/PTO01 P30/PTO00 P87/PTO11 P86/PTO10 Note SCL /P85/PWM3 Note SDA /P84/PWM2 P83/ROTC P82/HASW
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
P80 P57 P56 P55 P54 P53 P52 P51 P50 VSS VDD P47 P46 P45 P44 P43 P42 P41 P40 P07
CSYNCIN/P103 REEL0IN/INTP3/P102 REEL1IN/P101 DFGIN DPGIN/P100 CFGCPIN CFGAMPO CFGIN AVDD1 AVSS1 VREFC CTLOUT2 CTLOUT1 CTLIN RECCTLRECCTL+ CTLDLY AVSS2 ANI11/P113 ANI10/P112
ANI9/P111 ANI8/P110 P77/ANI7 P76/ANI6 P75/ANI5 P74/ANI4 P73/ANI3 P72/ANI2 P71/ANI1 P70/ANI0 AVREF AVDD2 P96 P95/KEY4 P94/KEY3 P93/KEY2 P92/KEY1 P91/KEY0 P90/ENV NMI/P20 INTP0/P21 INTP1/P22 INTP2/23 P00 P01 P02 P03 P04 P05 P06
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
Caution Directly connect the IC (Internally Connected) pins to VSS.
6
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
ANI0-ANI11 AVDD1, AVDD2 AVSS1, AVSS2 AVREF BUSY BUZ CFGAMPO CFGCPIN CFGIN CFGMON CLO CSYNCIN CTLDLY CTLIN CTLMON DFGIN DFGMON DPGIN DPGMON ENV HASW HWIN IC INTP0-INTP3 KEY0-KEY4 NMI P00-P07 Note : Analog Input : Analog Power Supply : Analog Ground : Analog Reference Voltage : Serial Busy : Buzzer Output : Capstan FG Amplifier Output : Capstan FG Capacitor Input : Analog Unit Input : Capstan FG Monitor : Clock Output : Analog Unit Input : Control Delay Input : CTL Amplifier Input Capacitor : CTL Amplifier Monitor : Analog Unit Input : DFG Monitor : Analog Unit Input : DPG Monitor : Envelope Input : Head Amplifier Switch Output : Hardware Timer External Input : Internally Connected : Interrupt From Peripherals : Key Return : Nonmaskable Interrupt : Port0 P20-P23 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P80, P82-P87 P90-P96 P100-P103 P110-P113 PTO00-PTO02, PTO10, PTO11 PWM0-PWM5 REEL0IN, REEL1IN RESET ROTC SCK1, SCK2 SCLNote SDANote SI1, SI2 SO1, SO2 STRB VDD VREFC VSS X1, X2 XT1, XT2 : Programmable Timer Output : Pulse Width Modulation Output : Analog Unit Input : Reset : Chrominance Rotate Output : Serial Clock : Serial Clock : Serial Data : Serial Input : Serial Output : Serial Strobe : Power Supply : Reference Amplifier Capacitor : Ground : Crystal (Main System Clock) : Crystal (Subsystem Clock) : Port2 : Port3 : Port4 : Port5 : Port6 : Port7 : Port8 : Port9 : Port10 : Port11
RECCTL+, RECCTL- : RECCTL Output/PBCLT Input
CTLOUT1, CTLOUT2 : CTL Amplifier Output
Pins SCL and SDA are provided for the PD784928Y subseries only.
Data Sheet U12255EJ2V0DS00
7
PD784927, 784928, 784927Y, 784928Y
INTERNAL BLOCK DIAGRAM
NMI INTP0-INTP3
INTERRUPT CONTROL SYSTEM CONTROL
PWM0-PWM5 PTO00-PTO02 PTO10, PTO11 SUPER TIMER UNIT CLOCK OUTPUT BUZZER OUTPUT VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTLCTLDLY DFGMON DPGMON CFGMON CTLMON AVDD1, AVDD2 AVSS1, AVSS2 AVREF AN10-AN11
VDD VSS X1 X2 XT1 XT2 RESET CLO BUZ
KEY INPUT
KEY0-KEY4
P00-P07 78K/IV 16-BIT CPU CORE (RAM: 512 bytes) REAL-TIME OUTPUT PORT P80, P82, P83 PORT0 PORT2 ANALOG UNIT & A/D CONVERTER RAM ROM PORT3 PORT4 PORT5 P00-P07 P20-P23 P30-P37 P40-P47 P50-P57 P60-P67 P70-P77 P80, P82-P87 P90-P96 P100-P103 P110-P113
SI1 SO1 SCK1
SERIAL INTERFACE 1
PORT6 PORT7
SI2/BUSY SO2 SCK2 STRB
SERIAL INTERFACE 2
PORT8 PORT9
SDA SCL
SERIAL Note INTERFACE 3
PORT10 PORT11
Note
Only the PD784928 subseries supports I2C bus interface.
Remark Internal ROM and RAM capacities differ depending on the product.
8
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
SYSTEM CONFIGURATION EXAMPLE
* Video camera
PD784927
DFG DPG Drum motor M Driver DFGIN DPGIN PORT PWM0 PORT SCK1 SI1 SO1 INTP0 INTP0 SCK Cameracontrolling SO microcontroller SI PD784038 PORT PORT Key matrix
CFG
CFGIN
Capstan motor
M
Driver
PWM1 Camera block RECCTL+ PORT SCK2 SO2 BUSY CS CLK DATA BUSY
CTL head RECCTL-
LCD C/D
PD7225
Loading motor
M
Driver
PWM2 LCD display panel PORT
Audio/video signal processing circuit
Composite sync signal CSYNCIN Video head switch PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 Remote controller reception signal
PORT
STRB
CS CLK DATA BUSY STB
OSD
PD6461
Remote controller signal
INTP2
PORT +VDD +VDD
Mechanical block
PC2800A
Note
EEPROMTM SDA SDA SCL Other ICs SDA X1 X2 XT1 XT2 SCL
SCL
Note
16 MHz
32.768 kHz
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
Data Sheet U12255EJ2V0DS00
9
PD784927, 784928, 784927Y, 784928Y
* Stationary VCR
PD784927
DFG DPG Drum motor M Driver DFGIN DPGIN PORT SCK1 SI1 SO1 STB CLK FIPTM C/D DOUT PD16311 DIN
PWM0
CFG
CFGIN FIP Key matrix
Capstan motor
M
Driver
PWM1 PORT SCK2 SO2 RECCTL+ CS OSD CLK PD6464A DATA
CTL head RECCTLPORT Composite sync signal Audio/video signal CSYNCIN Video head switch processing circuit PTO00 Audio head switch PTO01 Pseudo vertical sync signal P80 PWM5 PORT M Reel motor M Driver Reel FG1 PWM4 INTP2 REEL1IN +VDD +VDD EEPROM SDA
Note
Loading motor
M
Driver
PWM2
Reel FG0
REEL0IN Tuner
Driver
PWM3 PORT Remote controller reception signal Mechanical block Remote controller signal
PC2800A
SDA SCL Other ICs
SCL
Note
Low frequency oscillation mode X1 X2 XT1
SDA XT2 SCL
8 MHz
32.768 kHz
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
10
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
CONTENTS
1. DIFFERENCE BETWEEN PD784928 SUBSERIES AND 784928Y SUBSERIES .................... 12 2. PIN FUNCTION ............................................................................................................................... 13
2.1 2.2 2.3 Port Pins ................................................................................................................................................ Pins Other Than Port Pins .................................................................................................................. I/O Circuits of Pins and Processing of Unused Pins ...................................................................... 13 14 16
3. INTERNAL BLOCK FUNCTION ..................................................................................................... 19
3.1 CPU Registers ...................................................................................................................................... 3.1.1 3.1.2 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 General-purpose registers ......................................................................................................... Other CPU registers ................................................................................................................... 19 19 20 21 24 30 31 35 41 44 45 50 51 52
Memory Space ...................................................................................................................................... Special Function Registers (SFRs) ................................................................................................... Ports ....................................................................................................................................................... Real-Time Output Port ......................................................................................................................... Super Timer Unit .................................................................................................................................. Serial Interface ..................................................................................................................................... A/D Converter ....................................................................................................................................... VCR Analog Circuits ............................................................................................................................
3.10 Watch Function .................................................................................................................................... 3.11 Clock Output Function ........................................................................................................................ 3.12 Buzzer Output Function ......................................................................................................................
4. INTERNAL/EXTERNAL CONTROL FUNCTION ........................................................................... 53
4.1 Interrupt Function ................................................................................................................................ 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.3 4.4 Vectored interrupt ....................................................................................................................... Context switching ....................................................................................................................... Macro service ............................................................................................................................. Application example of macro service ...................................................................................... 53 56 56 57 59 62 64 65
Standby Function ................................................................................................................................. Clock Generation Circuit ..................................................................................................................... Reset Function .....................................................................................................................................
5. INSTRUCTION SET ........................................................................................................................ 66 6. ELECTRICAL SPECIFICATIONS .................................................................................................. 70 7. PACKAGE DRAWING .................................................................................................................... 85 8. RECOMMENDED SOLDERING CONDITIONS ............................................................................. 87 APPENDIX A. DEVELOPMENT TOOLS ............................................................................................ 88 APPENDIX B. RELATED DOCUMENTS ............................................................................................ 91
Data Sheet U12255EJ2V0DS00
11
PD784927, 784928, 784927Y, 784928Y
1. DIFFERENCE BETWEEN PD784928 SUBSERIES AND 784928Y SUBSERIES
The PD78F4928 and 78F4928Y are based on the PD784927 and 784927Y and are provided with a 128K-byte flash memory instead of a mask ROM. Table 1-1 shows the differences between the products in the PD784928 subseries and 784928Y subseries. Table 1-1. Differences between PD784928 Subseries and 784928Y Subseries
Part Number Item Internal ROM
PD784927, PD784927Y
Mask ROM 96K bytes
PD784928, PD784928Y
PD78F4928, PD78F4928Y
Flash memory
128K bytes 3584 bytes Provided
Internal RAM Internal memory capacity select register (IMS) IC pin VPP pin Electrical characteristics
2048 bytes Not provided
Provided Not provided Refer to the Data Sheet of each product.
Not provided Provided
12
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
2. PIN FUNCTION
2.1 Port Pins
Pin Name P00-P07 I/O I/O Shared with: Real-time output port NMI INTP0-INTP2 I/O PTO00-PTO02 SI2/BUSY SO2 SCK2 PWM1, PWM0 I/O -- 8-bit I/O port (port 4). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors. * Can directly drive LED. 8-bit I/O port (port 5). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors. 8-bit I/O port (port 6). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors. Function 8-bit I/O port (port 0). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors. 4-bit I/O port (port 2). * Can be connected with software pull-up resistors (P22 and P23 only). 8-bit I/O port (port 3). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors.
P20 P21-P23 P30-P32 P33 P34 P35 P36, P37 P40-P47
Input
P50-P57
I/O
--
P60 P61 P62 P63 P64 P65 P66 P67 P70-P77 P80 P82 P83 P84 P85 P86 P87 P90 P91-P95 P96 P100 P101 P102 P103 P110-P113
I/O
STRB/CLO SCK1/BUZ SO1 SI1 DFGMON/BUZ DPGMON/HWIN CFGMON/PWM4 CTLMON/PWM5
Input I/O
ANI0-ANI7 Real-time output port
8-bit input port (port 7) Pseudo VSYNC output HASW output ROTC output 7-bit I/O port (port 8). * Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors.
PWM2/SDANote PWM3/SCLNote PTO10 PTO11 I/O ENV KEY0-KEY4 -- Input DPGIN REEL1IN REEL0IN/INTP3 CSYNCIN Input ANI8-ANI11 4-bit input port (port 11). 7-bit I/O port (port 9).
* Can be set in input or output mode in 1-bit units. * Can be connected with software pull-up resistors. 4-bit input port (port 10).
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
Data Sheet U12255EJ2V0DS00
13
PD784927, 784928, 784927Y, 784928Y
2.2 Pins Other Than Port Pins (1/2)
Pin Name REEL0IN REEL1IN DFGIN DPGIN CFGIN CSYNCIN CFGCPIN CFGAMPO PTO00 PTO01 PTO02 PTO10 PTO11 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 HASW ROTC ENV SI1 SO1 SCK1 SI2 SO2 SCK2 BUSY STRB SDA SCL ANI0-ANI7 ANI8-ANI11 CTLIN CTLOUT1 CTLOUT2 RECCTL+, RECCTL- CTLDLY -- Output I/O I/O -- Output Output Input Input Output I/O Input Output I/O Input Output I/O I/O Analog input Output Output Output P30 P31 P32 P86 P87 P37 P36 P84/SDANote P85/SCLNote P66/CFGMON P67/CTLMON P82 P83 P90 P63 P62 P61/BUZ P33/BUSY P34 P35 P33/SI2 P60/CLO P84/PWM2 P85/PWM3 P70-P77 P110-P113 -- -- -- -- -- CTL amplifier input capacitor connection CTL amplifier output Logic signal input/CTL amplifier output RECCTL signal output/PBCTL signal input External time constant connection (for RECCTL rewriting) Head amplifier switch signal output Chrominance rotation signal output Envelope signal input Serial data input (serial interface channel 1) Serial data output (serial interface channel 1) Serial clock I/O (serial interface channel 1) Serial data input (serial interface channel 2) Serial data output (serial interface channel 2) Serial clock I/O (serial interface channel 2) Serial busy signal input (serial interface channel 2) Serial strobe signal output (serial interface channel 2) I2C bus data I/O I2C bus clock I/O Analog signal input of A/D converter PWM output of super timer unit P103 -- -- P100 -- I/O Input Shared with: P102/INTP3 P101 -- Drum FG, PFG input (ternary) Drum PG input Capstan FG input Composite SYNC input CFG comparator input CFG amplifier output Programmable timer output of super timer unit Reel FG input Function
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
Data Sheet U12255EJ2V0DS00
14
PD784927, 784928, 784927Y, 784928Y
2.2 Pins Other Than Port Pins (2/2)
Pin Name VREFC DFGMON DPGMON CFGMON CTLMON NMI INTP0-INTP2 INTP3 KEY0-KEY4 CLO BUZ Input Input Input Input Output Output I/O -- Output Shared with: -- P64/BUZ P65/HWIN P66/PWM4 P67/PWM5 P20 P21-P23 P102/REEL0IN P91-P95 P60/STRB P61/SCK1 P64/DFGMON HWIN RESET X1 X2 XT1 XT2 AVDD1 AVDD2 AVSS1 AVSS2 AVREF VDD VSS IC Input Input Input -- Input -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Crystal connection for subsystem clock oscillation. Crystal connection for watch clock oscillation Positive power supply to analog amplifier circuit Positive power supply to A/D converter and analog circuits input buffer GND of analog amplifier circuit GND of A/D converter and analog circuits input buffer Reference voltage input to A/D converter Positive power supply to digital circuits GND of digital circuits Internally connected. Directly connect this pin to VSS. P65/DPGMON -- -- External input of hardware watch counter Reset input Crystal connection for main system clock oscillation Key input signal input Clock output Buzzer output Function VREF amplifier AC connection Drum FG signal output Drum PG signal output CFG signal output CTL signal output Non-maskable interrupt request input External interrupt request input
Data Sheet U12255EJ2V0DS00
15
PD784927, 784928, 784927Y, 784928Y
2.3 I/O Circuits of Pins and Processing of Unused Pins Table 2-1 shows the types of the I/O circuits of the respective pins and processing of the unused pins. Figure 2-1 shows the circuits of the respective types. Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (1/2)
Pin P00-P07 I/O Circuit Type 5-A I/O I/O Recommended Connection of Unused Pins Input: Connect to VDD. Output: Leave unconnected. P20/NMI P21/INTP0 P22/INTP1, P23/INTP2 P30/PTO00-P32/PTO02 P33/SI2/BUSY P34/SO2 P35/SCK2 P36/PWM1, P37/PWM0 P40-P47 P50-P57 P60/STRB/CLO P61/SCK1/BUZ P62/SO1 P63/SI1 P64/DFGMON/BUZ P65/HWIN/DPGMON P66/PWM4/CFGMON P67/PWM5/CTLMON P70/ANI0-P77/ANI7 P80 P82/HASW P83/ROTC P84/PWM2/SDANote P85/PWM3/SCLNote P86/PTO10 P87/PTO11 P90/ENV P91/KEY0-P95/KEY4 P96 8-A 5-A 5-A 10-A 9 5-A Input I/O Connect to VSS. Input: Connect to VDD. Output: Leave unconnected. 8-A 5-A 8-A 5-A 8-A 5-A 2-A 5-A 8-A 5-A 8-A 5-A I/O 2 Input Connect to VDD. Connect to VDD or VSS. Connect to VDD. Input: Connect to VDD. Output: Leave unconnected.
Note
Pins SCL and SDA are provided for the PD784928Y subseries only.
16
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Table 2-1. I/O Circuits of Respective Pins and Processing of Unused Pins (2/2)
Pin P100/DPGIN I/O Circuit Type -- I/O Input Recommended Connection of Unused Pins When ENDRUM = 0 or ENDRUM = 1 and SELPGSEPA = 0: Connect to VSS. P101/REEL1IN P102/REEL0IN/INTP3 P103/CSYNCIN P110/ANI8-P113/ANI11 RECCTL+, RECCTL- DFGIN CFGIN, CFGCPIN CTLOUT1 CTLOUT2 -- -- Output I/O 9 -- -- Input I/O Input When ENCSYN = 0: Connect to VSS. Connect to VSS. When ENCTL = 0 and ENREC = 0: Connect to VSS. When ENDRUM = 0: Connect to VSS. When ENCAP = 0: Connect to VSS. Leave unconnected. When ENCTL = 0 and ENCOMP = 0: Connect to VSS. When ENCTL = 1: Leave unconnected. CFGAMPO CTLIN VREFC CTLDLY AVDD1, AVDD2 AVREF, AVSS1, AVSS2 RESET XT1 XT2 IC 2 -- -- -- Connect to VSS. Leave unconnected. Directly connect to VSS. -- -- -- -- Output -- Leave unconnected. When ENCTL = 0: Leave unconnected. When ENCTL = 0 and ENCAP = 0 and ENCOMP = 0: Leave unconnected. Leave unconnected. Connect to VDD. Connect to VSS. -- When ENREEL = 0: Connect to VSS.
Remark ENCTL ENREC ENDRUM ENCAP ENCSYN ENREEL ENCOMP
: bit 1 of amplifier control register (AMPC) : bit 7 of amplifier mode register 0 (AMPM0) : bit 2 of amplifier control register (AMPC) : bit 3 of amplifier control register (AMPC) : bit 5 of amplifier control register (AMPC) : bit 6 of amplifier control register (AMPC) : bit 4 of amplifier control register (AMPC)
SELPGSEPA : bit 2 of amplifier mode register 0 (AMPM0)
Data Sheet U12255EJ2V0DS00
17
PD784927, 784928, 784927Y, 784928Y
Figure 2-1. I/O Circuits of Respective Pins
Type 2
Type 8-A
VDD
IN
Pull-up enable VDD Data P-ch
P-ch
Schmitt trigger input with hysteresis characteristics
Type 2-A
VDD Pull-up enable Output disable N-ch
IN/ OUT
P-ch IN
Type 9
Schmitt trigger input with hysteresis characteristics
IN
P-ch N-ch
+ -
Comparator
Type 5-A
VDD Pull-up enable VDD Data P-ch IN/ OUT Output disable Input enable N-ch Pull-up Enable VDD Data P-ch IN/OUT Open drain Output disable N-ch VREF (Threshold voltage) Input enable P-ch
Type 10-A
VDD
P-ch
18
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
3. INTERNAL BLOCK FUNCTION
3.1 CPU Registers 3.1.1 General-purpose registers The PD784927 has eight banks of general-purpose registers. One bank consists of sixteen 8-bit general-purpose registers. Two of these 8-bit registers can be used in pairs as a 16-bit register. Four of the 16-bit general-purpose registers can be used to specify a 24-bit address in combination with an 8-bit address expansion register. These eight banks of general-purpose registers can be selected by software or context switching function. The general-purpose registers, except for the address expansion registers V, U, T, and W, are mapped to the internal RAM. Figure 3-1. Configuration of General-Purpose Register
A (R1) B (R3) R5 RP2 R7 RP3 V VVP (RG4) U UUP (RG5) R11 R9 VP (RP4)
X (R0) AX (RP0) C (R2) R4 R6 R8
BC (RP1)
R10 UP (RP5)
D (R13) E (R12) DE (RP6) TDE (RG6) W H (R15) L (R14) HL (RP7) WHL (RG7) ( ): absolute name
T
8 banks
Caution Although R4, R5, R6, R7, RP2, and RP3 can be used as X, A, C, B, AX, and BC registers, respectively, by setting the RSS bit of PSW to 1, do not use this function. The function of the RSS bit is planned to be deleted from the future models in the 78K/IV Series.
Data Sheet U12255EJ2V0DS00
19
PD784927, 784928, 784927Y, 784928Y
3.1.2 Other CPU registers (1) Program counter The program counter of the PD784927 is 20 bits wide. The value of the program counter is automatically updated as the program is executed.
19 PC
0
(2) Program status word This is a register that holds the various statuses of the CPU. Its contents are automatically updated as the program is executed.
PSWH PSW PSWL
15 14 13 12 11 UF RBS2 RBS1 RBS0 7 S 6 Z 5 RSS
Note
10
9
8
4 AC
3 IE
2 P/V
1 0
0 CY
Note
The RSS flag is provided to maintain compatibility with the microcomputers in the 78K/III Series. Always clear this flag to 0 except when the software of the 78K/III Series is used.
(3) Stack pointer This is a 24-bit pointer that holds the first address of the stack. Be sure to write 0 to the high-order 4 bits.
SP
23 00
0
20 0
0
20
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
3.2 Memory Space A memory space of 1M bytes can be accessed. The mapping of the internal data area (special function registers and internal RAM) can be selected by using the LOCATION instruction. The LOCATION instruction must be always executed after reset has been cleared, and cannot be used more than once. (1) When LOCATION 0H instruction is executed
Part Number Internal Data Area 0F700H-0FFFFH Internal ROM Area 00000H-0F6FFH 10000H-17FFFH 00000H-0F0FFH 10000H-1FFFFH
PD784927, 784927Y PD784928, 784928Y
0F100H-0FFFFH
Remark The area of the internal ROM overlapping the internal data area cannot be used when the LOCATION 0 instruction is executed.
Part Number Unusable Area 0F700H-0FFFFH (2304 bytes) 0F100H-0FFFFH (3840 bytes)
PD784927, 784927Y PD784928, 784928Y
(2) When LOCATION 0FH instruction is executed
Part Number Internal Data Area FF700H-FFFFFH FF100H-FFFFFH Internal ROM Area 00000H-17FFFH 00000H-1FFFFH
PD784927, 784927Y PD784928, 784928Y
Data Sheet U12255EJ2V0DS00
21
Figure 3-2. Memory Map of PD784927, 784927Y
When LOCATION 0H instruction is executed
FFFFFH
22
Cannot be used
18000H 17FFFH
When LOCATION 0FH instruction is executed
FFFFFH Special function registers (SFRs) FFFDFH Note 1 FFFD0H (256 bytes) FFF00H FFEFFH
0FEFFH
FFEFFH
General-purpose registers (128 bytes)
0FE80H 0FE7FH FFE80H FFE7FH FF700H FF6FFH
Internal RAM (2048 bytes)
Internal ROM
0FE3BH
(32768 bytes) 10000H 0FFFFH Special function registers (SFRs) 0FFDFH 0FFD0H Note 1 (256 bytes) 0FF00H 0FEFFH
Data Sheet U12255EJ2V0DS00
Macro service control 0FE06H word area (54 bytes) Data area (512 bytes)
FFE3BH FFE06H
Internal RAM (2048 bytes)
0F700H 0F6FFH
0FD00H 0FCFFH
FFD00H FFCFFH
Program/data area (1536 bytes)
0F700H 17FFFH 10000H
Note 2
FF700H 17FFFH
Cannot be used
PD784927, 784928, 784927Y, 784928Y
0F6FFH
Note 4
Program/data areaNote 3
01000H 00FFFH
Internal ROM (63232 bytes)
CALLF entry area (2K bytes)
00800H 007FFH 00080H 0007FH 00040H 0003FH
18000H 17FFFH
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (96K bytes)
Note 4
00000H
00000H
00000H
Notes 1. Accessed in external memory expansion mode 2. The 2304 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. When LOCATION 0H instruction is executed: 96000 bytes, when LOCATION 0FH instruction is executed: 98304 bytes 4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.
Figure 3-3. Memory Map of PD784928, 784928Y
When LOCATION 0H instruction is executed
FFFFFH
When LOCATION 0FH instruction is executed
FFFFFH Special function registers (SFRs) FFFDFH Note 1 FFFD0H (256 bytes) FFF00H FFEFFH
0FEFFH
FFEFFH
Cannot be used
General-purpose registers (128 bytes)
0FE80H 0FE7FH FFE80H FFE7FH FF100H FF0FFH
Internal RAM (3584 bytes)
20000H 1FFFFH
Internal ROM
0FE3BH
(65536 bytes) 10000H 0FFFFH Special function registers (SFRs) 0FFDFH 0FFD0H Note 1 (256 bytes) 0FF00H 0FEFFH
Data Sheet U12255EJ2V0DS00
Macro service control 0FE06H word area (54 bytes) Data area (512 bytes)
FFE3BH FFE06H
Internal RAM (3584 bytes)
0F100H 0F0FFH
0FD00H 0FCFFH
FFD00H FFCFFH
Program/data area (3072 bytes)
0F100H 1FFFFH 10000H
Note 2
PD784927, 784928, 784927Y, 784928Y
FF100H 1FFFFH
Cannot be used
0F0FFH
Note 4
Program/data areaNote 3
01000H 00FFFH
Internal ROM (61696 bytes)
CALLF entry area (2K bytes)
00800H 007FFH 00080H 0007FH 00040H 0003FH
20000H 1FFFFH
CALLT table area (64 bytes) Vector table area (64 bytes)
Internal ROM (128K bytes)
Note 4
00000H
00000H
00000H
Notes 1. Accessed in external memory expansion mode 2. The 3840 bytes in this area can be used as an internal ROM only when the LOCATION 0FH instruction is executed. 3. When LOCATION 0H instruction is executed: 127232 bytes, when LOCATION 0FH instruction is executed: 131072 bytes
23
4. Base area or entry area for reset or interrupt. Excluding the internal RAM for reset.
PD784927, 784928, 784927Y, 784928Y
3.3 Special Function Registers (SFRs) Special function registers are assigned special functions and mapped to a 256-byte space of addresses FF00H through FFFFH. These registers include mode registers and control registers that control the internal peripheral hardware units. Caution Do not access an address to which no SFR is assigned. If such an address is accessed by mistake, the PD784927 may be deadlocked. This deadlock can be cleared only by reset input. Table 3-1 lists the special function registers (SFRs). The meanings of the symbols in this table are as follows: * Symbol .................................... Abbreviation of an SFR. This abbreviation is reserved for NEC's assembler (RA78K4). With a C compiler (CC78K4), the abbreviation can be used as sfr variable by the #pragma sfr instruction. * R/W ......................................... Indicates whether the SFR in question can be read or written. R/W : Read/write R W : Read only : Write only
* Bit length ................................. Indicates the bit length (word length) of the SFR. * Bit units for manipulation ....... Indicates bit units in which the SFR in question can be manipulated. An SFR that can be manipulated in 16-bit units can be used as the operand sfrp of an instruction. Specify an even address to manipulate this SFR. An SFR that can be manipulated in 1-bit units can be used for a bit manipulation instruction. * After clearing reset ................. Indicates the status of each register immediately after clearing reset. Caution The addresses shown in Table 3-1 are used when the LOCATION 0H instruction is executed. Add "F0000H" to the address values shown in the table when the LOCATION 0FH instruction is executed.
24
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (1/5)
Address Special Function Register (SFR) Name Symbol R/W Bit Length FF00H FF02H FF03H FF04H FF05H FF06H FF07H FF08H FF09H FF0AH FF0BH FF0EH FF0FH FF10H FF11H FF12H FF13H FF14H FF15H FF16H FF17H FF18H FF1AH FF1CH FF1EH FF20H FF23H FF24H FF25H FF26H FF28H FF29H FF2EH FF30H FF31H FF32H FF34H FF35H FF36H Port 0 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11 Port 0 buffer register L Port 0 buffer register H Timer 0 compare register 0 Event counter compare register 0 Timer 0 compare register 1 Event counter compare register 1 Timer 0 compare register 2 Event counter compare register 2 Timer 1 compare register 0 Event counter compare register 3 Timer 1 compare register 1 Timer 1 compare register 2 Timer 1 compare register 3 Timer 2 compare register 0 Port 0 mode register Port 3 mode register Port 4 mode register Port 5 mode register Port 6 mode register Port 8 mode register Port 9 mode register Real-time output port 0 control register Timer counter 0 Event counter Timer counter 1 Free running counter (bits 0-15) Free running counter (bits 16-21) Timer counter 2 P0 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P0L P0H CR00 ECC0 CR01 ECC1 CR02 ECC2 CR10 ECC3 CR11 CR12 CR13 CR20 PM0 PM3 PM4 PM5 PM6 PM8 PM9 RTPC TM0 EC TM1 FRCL FRCH TM2 R R/W R W R/W W R/W W R/W W R/W R R/W R/W R R R/W R/W R R/W 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 16 8 16 8 16 8 16 16 16 16 8 8 8 8 8 8 8 8 16 8 16 16 8 16 -- -- -- -- -- -- -- -- -- -- 0000H 00H Cleared to 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- FDH 7FH 00H Cleared to 0 FFH -- -- -- -- -- -- -- -- Bit Units for Manipulation After Clearing 1 bit 8 bits 16 bits -- -- -- -- -- -- -- -- -- -- -- -- -- Cleared to 0 Reset Undefined
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
Data Sheet U12255EJ2V0DS00
25
PD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (2/5)
Address Special Function Register (SFR) Name Symbol R/W Bit Length FF38H FF39H FF3AH FF3BH FF3CH FF3DH FF3EH FF43H FF48H FF4BH FF4DH FF4EH FF4FH FF50H FF51H FF52H FF53H FF54H FF56H FF58H FF59H FF5AH FF5BH FF5CH FF5EH FF60H FF63H FF65H FF66H FF68H Timer control register 0 Timer control register 1 Timer control register 2 Timer control register 3 Timer counter 3 Timer control register 4 Timer counter 4 Port 3 mode control register Port 8 mode control register Control mode select register Trigger source select register 0 Pull-up resistor option register L Pull-up resistor option register H Input control register Up/down counter count register Event divider counter Capture mode register Timer counter 5 Timer 3 capture register 0 Timer 0 output mode register Timer 0 output control register Timer 1 output mode register Timer 1 output control register Timer 3 compare register 0 Timer 3 compare register 1 Port 8 buffer register L Up/down counter compare register Trigger source select register 1 Port 6 mode control register A/D converter mode register TMC0 TMC1 TMC2 TMC3 TM3 TMC4 TM4 PMC3 PMC8 CMS TRGS0 PUOL PUOH ICR UDC EDV CPTM TM5 CPT30 TOM0 TOC0 TOM1Note 1 TOC1 CR30 CR31 P8L UDCC TRGS1 PMC6 ADM ADMLNote 2 FF6AH FF6CH FF6EH FF6FH FF70H A/D conversion result register Hardware watch counter 0 Hardware watch counter 1 Watch mode register PWM control register 0 ADCR HW0 HW1 WM PWMC0 R R/W R R/W W R/W R/W W R/W W R R/W R R R/W R R/W R/W 8 8 8 8 16 8 16 8 8 8 8 8 8 8 8 8 8 16 16 8 8 8 8 16 16 8 8 8 8 16 8 8 16 16 8 8 -- -- -- -- -- -- -- -- -- -- -- Undefined Not affected by reset 00xx0x00 05H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000H 000x0x0x Undefined 00H -- -- -- -- -- -- xx000000 00H 80H 00H Cleared to 0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 10H Undefined Cleared to 0 00H Cleared to 0 -- -- -- Bit Units for Manipulation After Clearing 1 bit 8 bits 16 bits -- -- -- -- 00x00000 Cleared to 0 xx000000 Cleared to 0 00H Reset 00H
Notes 1. When the TOM1 is read, the write sequence of the REC driver is read (bits 0 and 1). 2. ADML is the low-order 8 bits of ADM and can be manipulated in 1- or 8-bit units. Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
26
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (3/5)
Address Special Function Register (SFR) Name Symbol R/W Bit Length FF71H FF72H FF73H FF74H FF75H FF76H FF77H FF78H FF79H FF7AH FF7BH FF7CH FF7DH FF7EH FF80H FF82H FF84H FF85H FF86H FF88H FF89H FF8AH FF8CH FF8EH FF90H FF91H FF94H FF95H FF96H FF97H FF98H FF99H FF9AH FF9BH FFA0H FFA1H FFA2H FFA3H External interrupt mode register External capture mode register 1 External capture mode register 2 VISS detection circuit control register INTM0 INTM1 INTM2 VDC 8 8 8 8 -- -- -- -- 000000x0 00H VISS detection circuit shift register 1 VSFT1 16 -- -- PWM control register 1 PWM0 modulo register PWM2 modulo register PWM1 modulo register PWM3 modulo register PWM5 modulo register PWM4 modulo register Event divider control register Clock output mode register Timer 4 capture/compare register 0 Clock control register Timer 4 capture register 1 Capture/compare control register Timer 5 compare register I2C control register I2C clock select register PWMC1 PWM0 PWM2 PWM1 PWM3 PWM5 PWM4 EDVC CLOM CR40 CC CR41 CRC CR50 IICC IICCL CSIM1 SIO1 SVA CSIM2 SIO2 CSIC2 IICS IIC AMPM2 HAPC AMPC AMPM0 AMPM1 CTLM VSFT0 R R/W R W R/W W R/W R/W 8 16 8 16 8 16 8 8 8 16 8 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0000H Undefined 00H Undefined 00H -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit Units for Manipulation After Clearing 1 bit 8 bits 16 bits -- Reset 15H 0000H 00H 0000H 00H 0000H 00H Cleared to 0 00H Cleared to 0 00H Cleared to 0 00H Cleared to 0 00H
Serial mode register 1 Serial shift register 1 Slave address register Serial mode register 2 Serial shift register 2 Serial control register 2 I2C bus status registerNote I2C bus shift registerNote Amplifier mode register 2 Head amplifier switch output control register Amplifier control register Amplifier mode register 0 Amplifier mode register 1 Gain control register VISS detection circuit shift register 0
Note
These registers are provided for the PD784928Y subseries only.
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
Data Sheet U12255EJ2V0DS00
27
PD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (4/5)
Address Special Function Register (SFR) Name Symbol R/W Bit Length FFA4H FFA5H FFA6H FFA7H FFA8H FFAAH FFACH FFADH FFAEH FFAFH FFB0H FFB1H FFB2H FFB3H FFB4H FFB5H FFB6H FFB7H FFB8H FFB9H FFBAH FFBBH FFBDH FFBEH FFBFH FFC0H FFC4H FFCEH FFCFH FFE0H FFE1H FFE2H FFE3H FFE4H FFE5H FFE6H FRC capture register 0L FRC capture register 0H FRC capture register 1L FRC capture register 1H FRC capture register 2L FRC capture register 2H FRC capture register 3L FRC capture register 3H FRC capture register 4L FRC capture register 4H FRC capture register 5L FRC capture register 5H VSYNC separation circuit control register VSYNC separation circuit up/down counter register VSYNC separation circuit compare register Standby control register Execution speed select register CPU clock status register Oscillation stabilization time specification register Interrupt control register (INTP0) Interrupt control register (INTCPT3) Interrupt control register (INTCPT2) Interrupt control register (INTCR12) Interrupt control register (INTCR00) Interrupt control register (INTCLR1) Interrupt control register (INTCR10) VISS detection circuit up/down counter register VUDC value setting register Key interrupt control register VISS pulse pattern setting register In-service priority register Interrupt mode control register Interrupt mask flag register VUDC VUDST KEYC VPS ISPR IMC MK0L MK0H MK1L MK1H CPT0L CPT0H CPT1L CPT1H CPT2L CPT2H CPT3L CPT3H CPT4L CPT4H CPT5L CPT5H VSC VSUDC VSCMP STBC MM PCS OSTS PIC0 CPTIC3 CPTIC2 CRIC12 CRIC00 CLRIC1 CRIC10 W R W R/W R/W R MK1 MK0 R R/W R/W 8 8 8 8 8 8 8 8 8 8 16 8 16 8 16 8 16 8 16 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 43H FFH 0011x000 20H 00H 00H -- -- -- -- -- -- -- -- -- -- Cleared to 0 -- Bit Units for Manipulation After Clearing 1 bit -- -- 8 bits 16 bits -- -- -- -- -- -- 80H FFH 70H 00H Reset 00H
Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
28
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Table 3-1. Special Function Registers (5/5)
Address Special Function Register (SFR) Name Symbol R/W Bit Length FFE7H FFE8H FFE9H FFEAH FFEBH FFECH FFEDH FFEEH FFEFH Interrupt control register (INTCR01) Interrupt control register (INTCR02) Interrupt control register (INTCR11) Interrupt control register (INTCPT1) Interrupt control register (INTCR20) Interrupt control register (INTIIC)Note 1 CRIC01 CRIC02 CRIC11 CPTIC1 CRIC20 IICIC TBIC ADIC PIC2 CRIC40 UDCIC CRIC30 CRIC50 CRIC13 CSIIC1 WIC VISIC PIC1 PIC3 CSIIC2 8 8 8 8 8 8 8 8 8 8 -- -- -- -- -- -- -- -- -- -- x1000011 43H R/W 8 8 8 8 8 8 8 8 8 Bit Units for Manipulation After Clearing 1 bit 8 bits 16 bits -- -- -- -- -- -- -- -- -- Reset 43H
Interrupt control register (INTTB) Interrupt control register (INTAD) Interrupt control register Interrupt control register (INTP2)Note 2 (INTCR40)Note 2
FFF0H FFF1H FFF2H FFF3H FFF4H FFF5H FFF6H FFF7H FFF8H FFFAH
Interrupt control register (INTUDC) Interrupt control register (INTCR30) Interrupt control register (INTCR50) Interrupt control register (INTCR13) Interrupt control register (INTCSI1) Interrupt control register (INTW) Interrupt control register (INTVISS) Interrupt control register (INTP1) Interrupt control register (INTP3) Interrupt control register (INTCSI2)
Notes 1. PD784928Y subseries only. 2. PIC2 and CRIC40 are at the same address (register). Remark Cleared to 0: Counter is initialized to 0 within 16 clocks after the reset signal has been cleared (the contents before initialization are undefined).
Data Sheet U12255EJ2V0DS00
29
PD784927, 784928, 784927Y, 784928Y
3.4 Ports The PD784927 is provided with the ports shown in Figure 3-3. Table 3-2 shows the function of each port. Figure 3-4. Port Configuration
P00 Port 0 P07 P20 Port 2 P23 P30 Port 3 P37
P60 Port 6 P67 P70-P77 P80 P82 Port 8 P87 P90 8 Port 7
P40 Port 4 P47 P50 Port 5 P110 P57 P113 P96 P100
Port 9
Port 10 P103
Port 11
Table 3-2. Port Function
Name Port 0 Pin Name P00-P07 Function Can be set in input or output mode in 1-bit units. Port 2 P20-P23 Input port Specification of Pull-up Resistor Pull-up resistors are connected to all pins in input mode. Pull-up resistors are connected to pins P22 and P23. Pull-up resistors are connected to all pins in input mode.
Port 3
P30-P37
Can be set in input or output mode in 1-bit units. Can be set in input or output mode in 1-bit units. Can directly drive LED. Can be set in input or output mode in 1-bit units. Input port Can be set in input or output mode in 1-bit units. Input port
Port 4
P40-P47
Port 5 Port 6 Port 7 Port 8 Port 9 Port 10 Port 11
P50-P57 P60-P67 P70-P77 P80, P82-P87 P90-P96 P100-P103 P110-P113
Pull-up resistor is not provided. Pull-up resistors are connected to all pins in input mode. Pull-up resistor is not provided.
30
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
3.5 Real-Time Output Port A real-time output port consists of a port output latch and a buffer register (refer to Figure 3-5). The function to transfer the data prepared in advance in the buffer register to the output latch when a trigger such as a timer interrupt occurs, and output the data to an external device is called a real-time output function. A port used in this way is called a real-time output port (RTP). Table 3-3 shows the real-time output ports of the PD784927. Table 3-4 shows the trigger sources of RTPs. Figure 3-5. Configuration of RTP
Buffer register Output trigger Port output latch
Port
Table 3-3. Bit Configuration of RTP
RTP Shared with: Number of Bits of Real-Time Output Data RTP0 Port 0 4 bits x 2 channels or 8 bits x 1 channel RTP8 Port 8 1 bit x 1 channel and 2 bits x 1 channel 1-bit units Pseudo VSYNC output: 1 channel (RTP80) Head amplifier switch: 1 channel (RTP82) Chrominance rotation signal output: 1 channel (RTP83) Number of Bits That Can Be Specified as RTP 4-bit units -- Remark
Table 3-4. Trigger Sources of RTP
Trigger Source RTP RTP0 High-order 4 bits Low-order 4 bits All 8 bits RTP8 Bit 0 Bits 2 and 3 Note 1 Note 2 INTCR00 INTCR01 INTCR02 INTCR13 INTCR50 INTP0 Remark
Notes 1. Select one of the four trigger sources. 2. When the real-time output port mode is set by the port mode control register 8 (PMC8), the HASW and ROT-C signals that are set by the head amplifier switch output control register (HAPC) are directly output. The HASW and ROT-C signals are synchronized with HSW output (TM0-CR00 coincidence signal). However, the set signal is output immediately when the HAPC register is rewritten.
Data Sheet U12255EJ2V0DS00
31
PD784927, 784928, 784927Y, 784928Y
Figures 3-6 and 3-7 show the block diagrams of RTP0 and RTP8. Figure 3-8 shows the types of RTP output trigger sources. Figure 3-6. Block Diagram of RTP0
Internal bus
8 4 4
Real-time output port 0 control register (RTPC)
Buffer register P0H P0L
4 4
8
INTP0 INTCR01 INTCR02
Output trigger Control circuit
Output latch (P0)
P07
P00
Remark INTCR01: TM0-CR01 coincidence signal INTCR02: TM0-CR02 coincidence signal Figure 3-7. Block Diagram of RTP8
Internal bus 8 Head amplifier output control register (HAPC) SEL SEL SEL PB PB PB 00 ROTC HASW ENV MOD2 MOD1 MOD0 TRGP80 HASW, ROT-C TM0-CR00 control circuit coincidence signal PMC80 0 PMC82 PMC83 PMC8 Output latch (P8) 8 Port 8 buffer register L (P8L) SEL 0 0 0 P8L4 P8L2 0 P8L0 MD80 Pseudo VSYNC output control circuit 8
HSYNC superimposition circuit P83 P82 P80
32
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Figure 3-8. Types of RTP Output Trigger Sources
Real-time output port 0 control register (RTPC) INTP0
TM0
Selector
Trigger of P0H Trigger of P0L
CR00 CR01 CR02 Selector TM1 Trigger of P80 Interrupt and timer output
Trigger of P82 and P83
CR10 CR11 Capture CR12
Interrupt and timer output
Trigger source select register 0 (TRGS0)
Interrupt CR13
TM5
CR50
Interrupt
Data Sheet U12255EJ2V0DS00
33
PD784927, 784928, 784927Y, 784928Y
RTP80 can output low-level, high-level, and high-impedance values real-time. Because RTP80 can superimpose a horizontal sync signal, it can be used to create pseudo vertical sync signal. When RTP80 is set in the pseudo VSYNC output mode, it repeatedly outputs a specific pattern when an output trigger occurs. Figure 3-9 shows the operation timing of RTP80. Figure 3-9. Example of Operation Timing of RTP80 (a) When HSYNC signal is superimposed
High level P80 High impedance Low level Trigger signal
(b) Pseudo VSYNC output mode
High level P80 High impedance Low level Trigger signal
34
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
3.6 Super Timer Unit The PD784927 is provided with a super timer unit that consists of the timers, and VCR special circuits such as a VISS detection circuit and a VSYNC separation circuit, etc., shown in Table 3-5. Table 3-5. Configuration of Super Timer Unit
Maximum Count Time Timer 0 TM0 (16-bit timer) 1 s 65.5 ms CR00 CR01 CR02 EC (8-bit counter) Free running counter CPT2 FRC (22-bit counter) 125 ns 524 ms -- -- ECC0, ECC1, ECC2, ECC3 CPT0 CPT1 Detects reference phase (to control drum phase) Detects phase of drum motor (to control drum phase) Detects speed of drum motor (to control drum speed) CPT3 Detects speed of capstan motor (to control speed of capstan motor) CPT4, CPT5 Timer 1 TM1 (16-bit timer) 1 s 65.5 ms CR10 Detects remaining tape for reel FG Playback: Creates internal reference signal Recording: Buffer oscillator in case VSYNC is missing CR11 CR12 Controls RECCTL output timing Detects phase of capstan motor (to control capstan phase) CR13 TM3 (16-bit timer) EDV (8-bit counter) Timer 2 TM2 (16-bit timer) Timer 4 TM4 (16-bit timer) CR41 2 s 2 s 131 ms CR40 Detects duty of remote controller signal (to decode remote controller signal) Measures cycle of remote controller signal (to de code remote controller signal) Timer 5 TM5 (16-bit timer) Up/down counter PWM output unit UDC (5-bit counter) -- -- -- PWM0, PWM1, PWM5 PWM2, PWM3, PWM4 8-bit resolution (carrier frequency: 62.5 kHz) 16-bit resolution (carrier frequency: 62.5 kHz) -- -- UDCC Creates linear tape counter 131 ms CR50 Can be used as interval timer (to control system) 1 s 65.5 ms CR20 Can be used as interval timer (to control system) 1 s or 1.1 s -- 65.5 ms or 71.5 ms -- CR30, CR31 CPT30 EDVC Controls VSYNC mask as noise preventive measures Controls duty detection timing of PBCTL signal Measures cycle of PBCTL signal Divides CFG signal frequency Controls delay of video head switching signal Controls delay of audio head switching signal Controls pseudo VSYNC output timing Creates internal head switching signal
Unit Name
Timer/Counter
Resolution
Register
Remark
Data Sheet U12255EJ2V0DS00
35
PD784927, 784928, 784927Y, 784928Y
(1) Timer 0 unit Timer 0 unit creates head switching signal and pseudo VSYNC output timing from the PG and FG signals of the drum motor. This unit consists of an event counter (EC: 8 bits), compare registers (ECC0 through ECC3), a timer (TM0: 16 bits), and compare registers (CR00 through CR02). A signal indicating coincidence between the value of timer 0 and the value of a compare register can be used as the output trigger of the real-time output port. (2) Free running counter unit The free running counter unit detects the speed and phase of the drum motor, and the speed and reel speed of the capstan motor. This unit consists of a free running counter (FRC), capture registers (CPT0 through CPT5), a VSYNC separation circuit, and a HSYNC separation circuit. (3) Timer 1 unit Timer 1 unit is a reference timer unit synchronized with the frame cycle and creates the RECCTL signal, detects the phase of the capstan motor, and detects the duty factor of the PBCTL signal. This unit consists of the following three groups: * Timer 1 (TM1), compare registers (CR10, CR11, and CR13), and capture register (CR12) * Timer 3 (TM3), compare registers (CR30 and CR31), and capture register (CPT30) * Event divider counter (EDV) and compare register (EDVC) The TM1-CR13 coincidence signal can be used for automatic unmasking of VSYNC or as the output trigger of the real-time output port.
36
Data Sheet U12255EJ2V0DS00
Figure 3-10. Block Diagram of Super Timer Unit (TM0, FRC, TM1)
Selector Selector Selector
Clear TM0 CR00 CR01 CR02
DPGIN Divider
Selector
Selector
Selector Writes 00H to EC
Mask
Output control circuit Output control circuit Output control circuit (Superimposition) RTP RTP, A/D INTCR00
PTO00 PTO01 INTCR01 PTO02 INTCR02
Selector
DFGIN
Clear EC ECC3 ECC2 ECC1 ECC0 F/F F/F
Analog circuit
RTP, A/D (Superimposition)
REEL1IN
Selector
Selector
Selector
Selector
Selector
PBCTL PTO10 PTO11
Selector
Data Sheet U12255EJ2V0DS00
HSYNC separation circuit
To P80
PD784927, 784928, 784927Y, 784928Y
Selector
Selector
CSYNCIN
VSYNC separation circuit
INTCLR1
Selector
Selector
FRC Capture Capture Capture Capture Capture Capture CPT0 CPT1 CPT2 CPT3 CPT4 CPT5
REEL0IN
Mask
INTCPT1 INTCPT2 INTCPT3
INTP3 Output control circuit PTO10 INTCR10 Output control circuit INTCR11 INTCR12 INTCR13 INTCR30 To PBCTL signal input block PTO11
CFGIN
Clear EDV EDVC Clear TM1 CR10 CR11 CR12 CR13
Clear TM3 CR30 CR31 Capture CPT30
Capture
CTL F/F
FFLVL
37
PD784927, 784928, 784927Y, 784928Y
(4) Timer 2 unit Timer 2 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM2) and a compare register (CR20). The timer is cleared when the TM2-CR20 coincidence signal occurs, and at the same time, an interrupt request is generated. Figure 3-11. Block Diagram of Timer 2 Unit
Clear TM2
CR20
INTCR20
(5) Timer 4 unit Timer 4 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM4), a capture/compare register (CR40), and a capture register (CR41). The value of the timer is captured to CR40/CR41 when the INTP2 signal is input. This timer can be used to decode a remote controller signal. Figure 3-12. Block Diagram of Timer 4 Unit
Mask Clear TM4
Selector
INTP2
CR40 CR41
INTCR40
(6) Timer 5 unit Timer 5 unit is a general-purpose 16-bit timer unit. This unit consists of a timer (TM5) and a compare register (CR50). The timer is cleared by the TM5-CR50 coincidence signal, and at the same time, an interrupt request is generated. Figure 3-13. Block Diagram of Timer 5 Unit
Clear TM5
CR50
INTCR50 RTP, A/D
38
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
(7) Up/down counter unit The up/down counter unit is a counter that realizes a linear time counter. This unit consists of an up/down counter (UDC) and a compare register (UDCC). The up/down counter counts up the rising edges of PBCTL and counts down the falling edges of PBCTL. When the value of the up/down counter coincides with the value of the compare register, or when the counter underflows, an interrupt request is generated. Figure 3-14. Block Diagram of Up/Down Counter Unit
SELUD PTO10 PTO11 Selector P77 EDVC output Selector
Selector
Selector
UP/DOWN UDC
PBCTL
UDCC
INTUDC
(8) PWM output unit The PWM output unit has three 16-bit accuracy output lines (PWM0, PWM1, and PWM5) and 8-bit accuracy output lines (PWM2 through PWM4). The carrier frequency of all the output lines is 62.5 kHz (fCLK = 8 MHz). PWM0 and PWM1 can be used to control the drum motor and capstan motor. Figure 3-15. Block Diagram of 16-Bit PWM Output Unit
(n = 0, 1, 5) Internal bus 16 PWMn 15 8 Reload 87 8 Reload Reload control 0 8
PWMC0 To selector
16 MHz
8-bit down counter
PWM pulse generation circuit 8-bit counter
Output control circuit
PWMn
1/256
RESET
Data Sheet U12255EJ2V0DS00
39
PD784927, 784928, 784927Y, 784928Y
Figure 3-16. Block Diagram of 8-Bit PWM Output Unit
Internal bus
PWM2
PWM3
PWM4
PWMC1
8-bit comparator
8-bit comparator
8-bit comparator Output control circuit
PWM4
16 MHz
PWM counter
Output control circuit
PWM3
Output control circuit
PWM2
(9) VISS detection circuit Figure 3-17. Block Diagram of VISS Detection Circuit
PBCTL
UP/DOWN CFG signal
Selector
fCLK/16 fCLK/64 fCLK/256
VUDC (8-bit up/down counter)
VUDST (VUDC value setting register)
VISS malfunction prevention circuit
VSFT0 (shift register 0)
VSFT1 (shift register 1) Coincidence
INTVISS
VPS (VISS pulse pattern setting register)
VCMP (compare register)
40
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
(10) VSYNC separation circuit Figure 3-18. Block Diagram of VSYNC Separation Circuit
CSYNC signal
fCLK/4
Digital noise rejection circuit
Selector
fCLK/8
VSUDC (8-bit up/down counter)
VSYNC F/F VSCMP (8-bit compare register)
Selector
S Q R
VSYNC
"00"
3.7 Serial Interface The PD784927 is provided with the serial interfaces shown in Table 3-6. Data can be automatically transmitted or received through these serial interfaces, when the macro service is used. Table 3-6. Types of Serial Interfaces
Name Serial interface channel 1 * Clocked serial interface (3-wire) * Bit length: 8 bits * Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) * MSB first/LSB first selectable Serial interface channel 2 * Clocked serial interface (3-wire) * Bit length: 8 bits * Clock rate: External clock/31.25 kHz/62.5 kHz/125 kHz/250 kHz/500 kHz/1 MHz (fCLK = 8 MHz) * MSB first/LSB first selectable * BUSY/STRB control function Serial interface channel 3 * I2C bus interface For multimaster Function
Data Sheet U12255EJ2V0DS00
41
PD784927, 784928, 784927Y, 784928Y
(1) Serial interface channels 1, 2 Figure 3-19. Block Diagram of Serial Interface Channel n (n = 1 or 2)
Internal bus
SIn /BUSY
Selector
SIOn register
CSIMn register
SOn
Serial clock counter SCKn
INTCSIn
Busy detection circuit
fCLK/8 fCLK/16 fCLK/32 fCLK/64 fCLK/128 fCLK/256
STRB
Strobe generation circuit
CSIC2 register
Internal bus
Remark The circuits enclosed in the broken line are provided to serial interface channel 2 only.
42
Data Sheet U12255EJ2V0DS00
Selector
PD784927, 784928, 784927Y, 784928Y
(2) Serial interface channel 3 (PD784928Y subseries only) This channel transfers 8-bit data with multiple devices using two lines: serial clock (SCL) and serial data bus (SDA). It conforms to the I2C bus format, and can output a "start condition", "data", and "stop condition" onto the serial data bus during transmission. This data is automatically detected by hardware during reception. SCL and SDA are open-drain output pins and therefore, must be connected with a pull-up resistor. Figure 3-20. Serial Interface Channel 3
+VDD +VDD Master CPU2 Slave CPU2 Address 1
Master CPU1 Slave CPU1
SDA SCL
Serial data bus Serial clock
SDA SCL
SDA SCL
Slave CPU3 Address 2
SDA SCL
Slave IC Address 3
SDA SCL
Slave IC Address N
Data Sheet U12255EJ2V0DS00
43
PD784927, 784928, 784927Y, 784928Y
3.8 A/D Converter The PD784927Y has an analog-to-digital (A/D) converter with 12 multiplexed analog inputs (ANI0 through ANI11). This A/D converter is of successive approximation type, and the conversion result is held by an 8-bit A/D conversion result register (ADCR) (conversion time: 10 s at fCLK = 8 MHz). A/D conversion can be started in the following two modes: * Hardware start : Conversion is started by a hardware triggerNote. * Software start : Conversion is started by setting a bit of the A/D converter mode register (ADM). After conversion has been started, the A/D converter operates in the following modes: * Scan mode : Sequentially selects more than one analog input to obtain data to be converted from all the pins. * Select mode: Use only one pin for analog input to obtain successive data to be converted. When the conversion result is transferred to ADCR, interrupt request INTAD is generated. By processing this interrupt with the macro service, the conversion result can be successively transferred to memory. A mode in which starting A/D conversion of the next pin is kept pending until the value of ADCR is read is also available. When this ode is used, reading the conversion result by mistake when timing is shifted because an interrupt is disabled can be prevented. Note A hardware trigger is the following coincidence signals, one of which is selected by the trigger source select register 1 (TRGS1): * TM0-CR01 coincidence signal * TM0-CR02 coincidence signal * TM1-CR13 coincidence signal * TM5-CR50 coincidence signal
44
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Figure 3-21. Block Diagram of A/D Converter
ADM.7 (CS) ANI0
Input selector
ANI1 ANI2 ANI3 . . . ANI11
Sample & hold circuit
Series resistor string 1 : ON Voltage comparator R/2
Tap selector
AVREF
. . .
R
Successive approximation register (SAR)
Selector
TM0-CR01 coincidence TM0-CR02 coincidence TM1-CR13 coincidence TM5-CR50 coincidence
Conversion trigger Control circuit Trigger enable 8 Delay detection circuit INTAD A/D conversion end interrupt
R/2 AVSS2
Trigger source select register 1 (TRGS1) A/D converter mode register (ADM) 16
A/D conversion result register (ADCR) 8 Internal bus
3.9 VCR Analog Circuits The PD784927 is provided with the following VCR analog circuits: * CTL amplifier * RECCTL driver (rewritable) * DPG amplifier * DFG amplifier * DPFG separation circuit (ternary separation circuit) * CFG amplifier * Reel FG comparator (2 channels) * CSYNC comparator
Data Sheet U12255EJ2V0DS00
45
PD784927, 784928, 784927Y, 784928Y
(1) CTL amplifier/RECCTL driver The CTL amplifier is used to amplify the playback control (PBCTL) signal that is reproduced from the CTL signal recorded on a VCR tape. The gain of the CTL amplifier is set by the gain control register (CTLM). Thirty-two types of gains can be set in increments of about 1.78 dB. The PD784927 is also provided with a gain control signal generation circuit that monitors the status of the amplifier output to perform optimum gain control by software. The gain control signal generation circuit generates a CTL detection flag that identifies the amplitude status of the CTL amplifier output. By using this CTL detection flag, the gain of the CTL amplifier can be optimized. The RECCTL driver writes a control signal onto a VCR tape. This driver operates in two modes: REC mode that is used for recording, and rewrite mode used to rewrite the VISS signal. The output status of the RECCTL pin is changed by hardware, by using the timer output from the super timer unit as a trigger. Figure 3-22. Block Diagram of CTL Amplifier and RECCTL Driver
ANI11 CTLDLY TOM1.4-TOM1.6
RECCTL driver
RECCTL-
CTL head
VREF AMPC. 1 + -
AMPC. 1 CTLIN CTLOUT1 CTLM. 0-CTLM. 4 CTLOUT2 Waveform shaping circuit PBCTL signal (to timer unit) CTLMON (to P67) + Gain control signal generation circuit CTL detection flag L (AMPM0. 1) CTL detection flag S (AMPM0. 3) CTL detection flag clear (1 write to AMPM0. 6)
46
Data Sheet U12255EJ2V0DS00
Selector
RECCTL+
TM1-CR11 coincidence signal TM1-CR13 coincidence signal TM3-CR30 coincidence signal
PD784927, 784928, 784927Y, 784928Y
(2) DPG amplifier, DFG amplifier, and DFPG separation circuit The DPG amplifier converts the drum PG (DPG) signal that indicates the phase information of the drum motor into a logic signal. The DFG amplifier amplifies the drum FG (DFG) signal that indicates the speed information of the drum motor. The DPFG separation circuit (ternary separation circuit) separates a drum PFG (DPFG) signal having speed and phase information into a DFG and DPG signals. Figure 3-23. Block Diagram of DPG Amplifier, DFG Amplifier, and DPFG Separation Circuit
AMPC.7 VREF AMPC.2 AMPM0.0 Drum PG signal DPGIN VREF + - DPG amplifier 0 : ON AMPM0.2 AMPC.2 Selector 1 0 DPG comparator
1 Selector DPG signal (to timer unit) DPGMON (to P65)
0
VREF
AMPC.2 + - DFG amplifier
AMPM0.0 Drum FG signal or drum PFG signal
DFGIN AMPM0.2 AMPM0.2 0 1 AMPC.2 DPFG separation circuit (ternary separation circuit) AMPM0.2 1 0 AMPC.2
Selector
1 Selector DFG signal (to timer unit) DFGMON (to P64)
0
Data Sheet U12255EJ2V0DS00
47
PD784927, 784928, 784927Y, 784928Y
(3) CFG amplifier The CFG amplifier amplifies the capstan FG (CFG) signal that indicates the speed information of the capstan motor. This amplifier consists of an operational amplifier and a comparator. The gain of the operational amplifier is set by using an external resistor. When the gain of the operational amplifier is set to 50 dB, the output duty accuracy of the CFG signal can be improved to 50.0 0.3%. Figure 3-24. Block Diagram of CFG Amplifier
VREF
AMPC.3 + CFG amplifier
Capstan FG signal CFGIN
-
CFGAMPO
AMPM0.0
VREF AMPC.3 CFG comparator
AMPC.3
CFGCPIN +
Selector
1
CFG signal (to timer unit) CFGMON (to P66)
0
(4) Reel FG comparators The reel FG comparator converts a reel FG signal that indicates the speed information of the reel motor into a logic signal. Two comparators, one for take-up and the other for supply, are provided. Figure 3-25. Block Diagram of Reel FG Comparators
VREF AMPC.6 AMPM0.0 1 REEL0IN Reel FG comparator 0 VREF AMPC.6 AMPM0.0 AMPC.6
Selector
Supply reel signal
Reel FG0 signal (to timer unit)
REEL1IN Reel FG comparator 0
Selector
Take-up reel signal
1 Reel FG1 signal (to timer unit)
48
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
(5) CSYNC comparator The CSYNC comparator converts the COMPSYNC signal into a logic signal. Figure 3-26. Block Diagram of COMPSYNC Comparator
VREF AMPM1.7 AMPC.5 AMPM0.0
Selector
AMPC.5
COMPSYNC signal CSYNCIN CSYNC comparator
1 CSYNC signal (to timer unit)
0
(6) Reference amplifier The reference amplifier generates a reference voltage (VREF) to be supplied to the internal amplifiers and comparators of the PD784927. Figure 3-27. Block Diagram of Reference Amplifier
AVDD1 +
ENCAP (AMPC.3)
VREFC
VREF (CFG amplifier)
AVSS1
+ VREF (CFG amplifier) ENCTL (AMPC.1) + VREF (CTL amplifier)
ENDRUM (AMPC.2) ENREEL (AMPC.6) ENCSYN (AMPC.5)
+ VREF DFG amplifier, DPG comparator, reel FG comparator, and CSYNC comparator)
Remark Multiple reference amplifiers are provided to assure the accuracy of the amplifiers and comparators.
Data Sheet U12255EJ2V0DS00
49
PD784927, 784928, 784927Y, 784928Y
(7) Analog circuit monitor function This function is to output the following signals to port pins, and is mainly used for debugging. * Comparator output of CTL amplifier CTLMON (multiplexed port: P67) * Comparator output of CFG amplifier CFGMON (multiplexed port: P66) * Comparator output of DPG amplifier DPGMON (multiplexed port: P65) * Comparator output of DFG amplifier DFGMON (multiplexed port: P64) 3.10 Watch Function The PD784927 has a watch function that counts the overflow signals of the watch timer by hardware. As the clock, the subsystem clock (32.768 kHz) is used. Because this watch function is independent of the CPU, it can be used even while the CPU is in the standby mode (STOP mode) or is reset. In addition, this function can be used at a low voltage of VDD = 2.7 V (MIN.). Therefore, by using only the watch function with the CPU set in the standby mode or reset, a watch operation can be performed at a low voltage and low current consumption. In addition, the watch function can also be used while the CPU is in the normal operation mode, because a dedicated counter is provided. The watch function can be used to count up to about 17 years of data. The hardware watch counters (HW0 and HW1) are shared with external input counters. These counters execute counting at the falling edge of input to the P65 pin, and can be used to count the HSYNC signals. Figure 3-28. Block Diagram of Watch Counter
PM65 PMC65 CMS5 Edge detection Pin level read WM.2 (enables/disables operation)
Selector
P65
P65
fXT (32.768 kHz)
0
13
Selector
1 0
WM.2 (enables/disables operation)
0 15 0 13
Watch timer Normal
1 Fast forward
0
HW0
HW1 WM.2
Selector
To NMI generation block
WM.1
Selector
Subclock BUZ signal WM.7
WM.6 INTW
WM.5 WM.4 WM.2
50
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
3.11 Clock Output Function The PD784927 can output a square wave (with a duty factor of 50%) to the P60/STRB/CLO pin as the operating clock for the peripheral devices or other microcomputers. To enable or disable the clock output, and to set the frequency of the clock, the clock output mode register (CLOM) is used. When setting the frequency, the division ratio can be set to fCLK/n (where n = 1, 2, 4, 8, 16, 32, 64, or 128) (fCLK = fOSC/2: fOSC is the oscillation frequency of the resonator). Figure 3-29 shows the block diagram of the clock output circuit. The clock output (CLO) pin is shared with P60 and STRB. Figure 3-29. Block Diagram of Clock Output Circuit
CLOM fCLK fCLK/2 fCLK/4
CLOM7
CLOM6 CLOM5
ENCLO
0
SELFRQ2 SELFRQ1 SELFRQ0
Selector
fCLK/16 fCLK/32 fCLK/64 fCLK/128
Selector
fCLK/8
1 P60/STRB/CLO
P60 (Output latch)
0
RESET
Remark fCLK: internal system clock Caution Do not use the clock output function in the STOP mode. Clear ENCLO (CLOM.4) to 0 in the STOP mode. Figure 3-30. Application Example of Clock Output Function
PD784927
PD7503A
LCD 24 CLO SCK1 SI1 SO1 System clock CL1 SCK SO SI
Data Sheet U12255EJ2V0DS00
51
PD784927, 784928, 784927Y, 784928Y
3.12 Buzzer Output Function The BUZ signal can be superimposed on P61 or P64. The buzzer output frequency can be generated from the subsystem clock frequency or main system clock frequency. Figure 3-31 shows the block diagram of the BUZ output circuit. The BUZ signal can be also used for trimming the subsystem clock. Figure 3-31. Block Diagram of BUZ Output Circuit
WM4 WM5 2.048 kHz
Selector
CMS4 WM7
Selector
4.096 kHz 32.768 kHz
CLOM7
P61 (Output latch)
0 P61/BUZ
1 0
Selector
BUZ output
CLOM5 CLOM6 fCLK/512 fCLK/1024 fCLK/2048 fCLK/4096
Selector
1
Selector
0 P64 (Output latch) 1 BUZ output
P64/BUZ
52
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
4. INTERNAL/EXTERNAL CONTROL FUNCTION
4.1 Interrupt Function The PD784927 has as many as 32 interrupt sources, including internal and external sources. For 28 sources, a high-speed interrupt processing mode such as context switching or macro service can be specified by software. Table 4-1 lists the interrupt sources.
Data Sheet U12255EJ2V0DS00
53
PD784927, 784928, 784927Y, 784928Y
Table 4-1. Interrupt Sources
Interrupt Request Priority Type Reset Nonmaskable Maskable 0 1 2 3 INTP0 INTP0 pin input edge PIC0 CPTIC3 CPTIC2 CRIC12 Yes Yes FE06H FE08H FE0AH FE0CH 0006H 0008H 000AH 000CH -- -- Name RESET NMI RESET pin input NMI pin input edge Trigger
Interrupt Control Register Name
Interrupt Request Source
Macro
Context Macro Service Address
Vector Table Address 0000H 0002H
Service Switching Control Word No No -- --
-- --
INTCPT3 EDVC output signal (CPT3 capture) INTCPT2 DFGIN pin input edge (CPT2 capture) INTCR12 PBCTL input edge/EDVC output signal (CR12 capture)
4 5 6 7 8 9 10
INTCR00 TM0-CR00 coincidence signal INTCLR1 CSYNCIN pin input edge INTCR10 TM1-CR10 coincidence signal INTCR01 TM0-CR01 coincidence signal INTCR02 TM0-CR02 coincidence signal INTCR11 TM1-CR11 coincidence signal INTCPT1 Pin input edge/EC output signal (CPT1 capture)
CRIC00 CLRIC1 CRIC10 CRIC01 CRIC02 CRIC11 CPTIC1
FE0EH FE10H FE12H FE14H FE16H FE18H FE1AH
000EH 0010H 0012H 0014H 0016H 0018H 001AH
11 12 13 14 15
INTCR20 TM2-CR20 coincidence signal INTIIC INTTB INTAD INTP2 End of I2 C bus transfer
CRIC20 IICICNote TBIC ADIC PIC2 CRIC40 UDCIC CRIC30 CRIC50 CRIC13 CSIIC1 WIC VISIC PIC1 PIC3 CSIIC2 -- No No
FE1CH FE1EH FE20H FE22H FE24H
001CH 001EH 0020H 0022H 0024H
Time base from FRC A/D converter conversion end INTP2 pin input edge
INTCR40 TM4-CR40 coincidence signal 16 17 18 19 20 21 22 23 24 25 Operand error Software -- -- -- -- -- INTUDC UDC-UDCC coincidence/UDC underflow
FE26H FE28H FE2AH FE2CH FE2EH FE30H FE32H FE34H FE36H FE3AH --
0026H 0028H 002AH 002CH 002EH 0030H 0032H 0034H 0036H 003AH 003CH
INTCR30 TM3-CR30 coincidence signal INTCR50 TM5-CR50 coincidence signal INTCR13 TM1-CR13 coincidence signal INTCSI1 INTW INTVISS INTP1 INTP3 INTCSI2 -- End of serial transfer (channel 1) Overflow of watch timer VISS detection signal INTP1 pin input edge INTP3 pin input edge End of serial transfer (channel 2) Illegal operand of MOV STBC, #byte or LOCATION instruction Execution of BRK instruction Execution of BRKCS instruction
-- -- Yes
-- --
003EH --
Note
PD784928Y subseries only.
Remark EVDC : Event divider compare register EC FRC : Event counter : Free running counter
Data Sheet U12255EJ2V0DS00
MSCW : Macro service control register
54
PD784927, 784928, 784927Y, 784928Y
Figure 4-1. Differences in Operation Depending on Interrupt Processing Mode
Macro service
Main routine
Macro service processing
Main routine
Context Note 1 switching Vectored Note 1 interrupt
Main routine
Note 2
Interrupt processing
Note 3
Main routine
Main routine
Note 4
SEL RBn
Interrupt processing
Restoring PC and PSW
Main routine
Vectored interrupt
Main routine
Note 4
Saving general-purpose register
Initializing general-purpose register
Interrupt processing
Restoring general-purpose register
Restoring PC and PSW
Main routine
Interrupt request generated
Notes 1. When the register bank switching function is used and when initial values are set in advance to the registers 2. Selecting a register bank and saving PC and PSW by context switching 3. Restoring register bank, PC, and PSW by context switching 4. Saves PC and PSW to stack and loads vector address to PC
Data Sheet U12255EJ2V0DS00
55
PD784927, 784928, 784927Y, 784928Y
4.1.1 Vectored interrupt When an interrupt request is acknowledged, an interrupt processing program is executed according to the data stored in the vector table area (the first address of the interrupt processing program created by the user). In addition, four levels of priorities can be specified by software. 4.1.2 Context switching When an interrupt request is generated or when the BRKCS instruction is executed, a specific register bank is selected by hardware, and execution branches to a vector address set in advance in the register bank. At the same time, the current contents of the program counter (PC) and program status word (PSW) are saved to the registers in the register bank. Because the contents of PC and PSW are not saved to the stack area, execution can be branched to an interrupt processing routine more quickly than the vectored interrupt. Figure 4-2. Context Switching Operation When Interrupt Request Is Generated
<7> 0H Register bank n (n = 0-7)
PC19-16 PC15-0
Register bank (0-7) A B R5 R7 X C R4 R6 VP UP D H E L <3> Switching register bank (RBS0-RBS2 n) <4> RSS 0 IE 0
<6> Exchange <2> Save Bits 8-11 of temporary register <5> Save V U T <1> Save PSW W
Temporary register
56
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
4.1.3 Macro service The macro service is a function to transfer data between the memory and a special function register (SFR) without intervention by the CPU. A macro service controller accesses the memory and SFR and directly transfers the data. Because the status of the CPU is not saved or restored, data can be transferred more quickly than context switching. The processing that can be executed with the macro service is described below. Figure 4-3. Macro Service
CPU
Memory
Read Write
Macro service controller
Write Read
SFR
Internal bus
(1) Counter mode In this mode, the value of the macro service counter (MSC) is decremented when an interrupt request occurs. This mode can be used to execute the division operation of an interrupt request or count the number of times an interrupt request has occurred. When the value of the macro service counter has been decremented to 0, a vectored interrupt occurs.
MSC
-1
(2) Compound data transfer mode When an interrupt request occurs, data are simultaneously transferred from an 8-bit SFR to memory, a 16bit SFR to memory (word), memory (byte) to an 8-bit SFR, and memory (word) to a 16-bit SFR (3 points MAX. for each transfer). This mode can also be used to exchange data, instead of transferring data. This mode can be used for automatic transfer/reception by the serial interface or automatic updating of data/ timing by the serial output port. When the value of the macro service counter reaches to 0, a vectored interrupt request occurs.
Memory
SFR<4>-1
SFR<4>-2 SFR<4>-3
SFR<3>-1
SFR<3>-2
SFR<3>-3
. . .
Internal bus
SFR<2>-1 SFR<2>-2 SFR<2>-3 SFR<1>-1 SFR<1>-2 SFR<1>-3
Internal bus
Data Sheet U12255EJ2V0DS00
57
PD784927, 784928, 784927Y, 784928Y
(3) Macro service type A When an interrupt request occurs, data is transferred from an 8-/16-bit SFR to memory (byte/word) or from memory (byte/word) to an 8-/16-bit SFR. Data is transferred the number of times set in advance by the macro service counter. This mode can be used to store the result of A/D conversion or for automatic transfer (or reception) by the serial interface. Because transfer data is stored at an address FE00H to FEFFH, if only a small quantity of data is to be transferred, the data can be transferred at high speeds. When the value of the macro service counter is decremented to 0, a vectored interrupt request occurs.
Data storage buffer (memory) Data n Data n - 1
Data storage buffer (memory) Data n Data n - 1
Data 2 Data 1
Data 2 Data 1
Internal bus
Internal bus
SFR
SFR
(4) Data pattern identification mode (VISS detection mode) This mode of macro service is for detection of the VISS signal and is used in combination with a pulse width detection circuit. When an interrupt request occurs, the content of bit 7 of an SFR (usually, TMC3) specified by SFR pointer 1 is shifted into the buffer area. At the same time, the data in the buffer area is compared with the data in the compare area. If the two data coincide, a vectored interrupt request is generated. When the value of the macro service counter is decremented to 0, a vectored interrupt request occurs. It can be specified by option that the value of an SFR (usually, CPT30) specified by SFR pointer 2 be multiplied by a coefficient and the result of this multiplication be stored to an SFR (usually, CR30) specified by SFR pointer 3 (this operation is to automatically update an identification threshold value when the tape speed fluctuates).
Buffer area (memory)
Compare area (memory)
Coefficient (memory)
CPT30 TM3
Coincidence
Multiplier
CR30
CTL F/F (bit 7 of TMC3) Vectored interrupt
58
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
4.1.4 Application example of macro service (1) Automatic transfer/reception of serial interface Automatic transfer/reception of 3-byte data by serial interface channel 1 Setting of macro service register: compound data transfer mode (exchange mode)
7 0
FE50H
High-order address
Macro service counter (MSC = 2) Memory pointer H (= FD) Macro service channel Memory pointer L (= 50) ddccbbaa (= 01000100B) SFR pointer <2> (SFRP2 = 85H) SFR pointer <4> (SFRP4 = 85H)
Channel pointer (= 50H) Macro service control word Mode register (= 10110011B) FE2EH Low-order address
(Before transfer) (Exchange 2)
SI1
Transmit data 3 FD52H SIO1 (FF85H) <3> Transmit data 2 FD51H <2> (Exchange 1) (Transmit data 1) FD50H <1> Transfer is started by writing transmit data 1 to SIO1 by software.
SO1
(After transfer) Receive data 2 FD51H
Receive data 1 FD50H (Receive data 3 is the data of SIO1.)
Data Sheet U12255EJ2V0DS00
59
PD784927, 784928, 784927Y, 784928Y
(2) Reception operation of serial interface Transfer of receive data by serial interface channel 1 (16 bytes) Setting of macro service mode register: macro service type A (1-byte data transfer from SFR to memory)
Internal RAM FE7FH MSC 0FH SFR pointer 85H Setting of number of transfers Low-order 8 bits of address of SIO1 register
Channel pointer (= 7FH) FE2EH Mode register (= 00010001B) Starts macro service when INTCSI1 occurs
SI1
SIO1 (FF85H)
60
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
(3) VISS detection operation Setting of macro service mode register: data pattern identification mode (with multiplication, 8-byte comparison)
CPT30 High-order address FE50H Macro service counter (MSC = FFH) SFR pointer 2 (SFRP2 = 56H) Coefficient (6EH: 43%) SFR pointer 3 (SFRP3 = 5CH) SFR pointer 1 (SFRP1 = 3BH) Buffer size specification register (64 bits: 8H) 1 8 bytes 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 Bit 7 0 TMC3 Multiplier CR30 TM3
0
0
0
0
0
0
0
0
1050H 8 bytes
Compare area pointer (high): 10H Compare area pointer (low): 50H Coincidence (vectored interrupt) Channel pointer (= 50H) FE0CH Mode register (= 00010100B) (CTL signal input edge detection interrupt) Low-order address
Data Sheet U12255EJ2V0DS00
61
PD784927, 784928, 784927Y, 784928Y
4.2 Standby Function The standby function is to reduce the power consumption of the chip and is used in the following modes:
Mode HALT mode Function Stops operating clock of CPU. Reduces average power consumption when used in combination with normal mode for intermittent operation Stops oscillator. Stops all internal operations of chip to minimize power consumption to leakage current only Stops main system clock with subsystem clock used as system clock. CPU can operate with subsystem clock to reduce current consumption Standby function in low power consumption mode. Stops operating clock of CPU. Reduces power consumption of overall system
STOP mode
Low power consumption mode
Low power consumption HALT mode
These modes are programmable. The macro service can be started in the HALT mode. Figure 4-4. Status Transition of Standby Function
Low power consumption mode (subsystem clock operation)
st ode ue
Sets low power consumption mode Restores normal operation
n st atio abiliz np eriod
Inter RES
Ma
Normal operation
En En
cro fo
do
se
rvi
do
fm
ne ro
ce
ac
pro se
req ssi
ce
ue
st
HAL
E
put
f os nd o
req
Tm
cil at
io
rvi
ng
Sets HAL
ce
rupt
RE
P2
pu
Set
req
I in
INT
r co
owe
ce
NM
W,
rvi
wp
INT
cro
s lo
Ma
Set
Low power consumption HALT mode (standby)
STOP mode (standby)
HALT mode (standby)
Unmasked interrupt request
Notes 1. NMI input means starting NMI by NMI pin input, watch interrupt, or key interrupt input. 2. Unmasked interrupt request
62
Data Sheet U12255EJ2V0DS00
En
do
fo
ne
pro
se
ce
ss
ing
Waits for stabilization of oscillation
NM I in
No
TO
t Note
inte
SE
mpt
Macro service
ue st
pt
ET in
T in
rru
ion
1
P
T
requ
put
nsu
sS
est
Note 2
pu
te 1
t
PD784927, 784928, 784927Y, 784928Y
Figure 4-5. Relations among NMI, Watch Interrupt, and Key Interrupt When STOP Mode Is Released
INTM0.0 Standby control block NMI
Selector
Latch Clear Interrupt control block
INTP1 INTP2 KEY0 KEY1 KEY2 KEY3 KEY4 Cleared when "0" is written to KEYC.7 Mask KEYC.6 Mask KEYC.5 Mask KEYC.4 SQ R WM.6 Cleared when "0" is written to KEYC.0
Selector
SQ R
KEYC.7
KEYC.0
Watch timer INTW (OVF) Divides INTW by 128 (HW0L.7)
Mask WM.3
Data Sheet U12255EJ2V0DS00
63
Selector
X2 16 MHz or 8 MHz
1/2
Selector
Oscillation stop From standby control block
fXX/4 (fXX/2)Note 1 fXX/2 (fXX)Note 1
Selector
64
PD784927
X1
Main system clock oscillation circuit
peripheral circuits. Figure 4-6 shows the configuration of this circuit.
4.3 Clock Generation Circuit
Figure 4-6. Block Diagram of Clock Generation Circuit
The clock generation circuit generates and controls the internal system clock (CLK) to be supplied to the CPU and
CC.7 STBC.4, 5 Low-frequency oscillation mode fXX Normal mode Oscillation stabilization timer 1/2 1/2 1/2 fXX/16 (fXX/8)Note 1 fXX/8 (fXX/4)Note 1 STBC.6
fCLK
CPU Peripheral hardware operation clockNote 2
XT1
Subsystem clock oscillation circuit
fXT
Watch timer
Hardware watch function Watch interrupt
Data Sheet U12255EJ2V0DS00
XT2 32.768 kHz
Oscillation stop STBC.7
PD784927, 784928, 784927Y, 784928Y
Notes 1. fXX: oscillation frequency, ( ): in low-frequency oscillation mode. 2. The peripheral hardware units that can operate with the subsystem clock have some restrictions. For details, refer to PD784928, 784928Y Subseries User's Manual-Hardware (U12648E).
PD784927, 784928, 784927Y, 784928Y
4.4 Reset Function When a low-level signal is input to the RESET pin, the system is reset, and each hardware unit is initialized (reset status). During the reset period, oscillation of the system clock is unconditionally stopped, so that the current consumption of the overall system can be reduced. When the RESET pin goes high, the reset status is cleared. After the count time of the oscillation stabilization timer (32.8 ms at 16 MHz or 65.6 ms at 8 MHz) has elapsed, the contents of the reset vector table are set to the program counter (PC), and execution branches to the address set to the PC, and the program is executed starting from the branch destination address. Therefore, execution can be reset and started from any address. Figure 4-7. Oscillation of Main System Clock during Reset Period
Main system clock oscillation circuit During reset, oscillation is unconditionally stopped. fCLT
RESET input
Oscillation stabilization timer count time
The RESET pin is provided with an analog delay noise rejection circuit to prevent malfunctioning due to noise. Figure 4-8. Accepting Reset Signal
Analog delay
Analog delay
Oscillation Analog stabilization delay time
RESET input
Internal reset signal
Internal clock
Data Sheet U12255EJ2V0DS00
65
PD784927, 784928, 784927Y, 784928Y
5. INSTRUCTION SET
(1) 8-bit instructions (( ): combination realized by using A as r) MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC, ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC, MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA
2nd Operand # byte A r r' 1st Operand A (MOV) ADDNote 1 (MOV) (XCH) MOV XCH (MOV)Note 6 MOV (XCH)Note 6 (XCH) (MOV) (XCH) saddr saddr' sfr !addr16 !!addr24 mem [saddrp] [%saddrg] MOV XCH ADDNote 1 r3 PSWL PSWH MOV (MOV) (XCH) (MOV) (XCH) RORNote 3 MULU DIVUW INC DEC saddr MOV (MOV)Note 6 MOV MOV ADDNote 1 sfr MOV MOV MOV ADDNote 1 (ADD)Note 1 ADDNote 1 INC DEC DBNZ PUSH POP CHKL CHKLA !addr16 !!addr24 mem [saddrp] [%saddrg] mem3 ROR4 ROL4 r3 PSWL PSWH B, C STBC, WDM [TDE+] MOV (MOV) (ADD)Note 1 MOVMNote 4 [TDE-] (MOV) (ADD)Note 1 MOVMNote 4 MOVBKNote 5 MOVBKNote 5 DBNZ MOV MOV MOV (MOV) ADDNote 1 MOV ADDNote 1 MOV ADDNote 1 (ADD)Note 1 ADDNote 1 XCH [WHL+] [WHL-] n NoneNote 2
(ADD)Note 1 (ADD)Note 1 (ADD)Notes 1,6 (ADD)Note 1 ADDNote 1 r MOV ADDNote 1 (MOV) (XCH) MOV XCH MOV XCH MOV XCH MOV XCH
(ADD)Note 1 (ADD)Note 1
(ADD)Note 1 ADDNote 1 ADDNote 1 ADDNote 1
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD. 2. Either the second operand is not used, or the second operation is not an operand address. 3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR. 4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM. 5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK. 6. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short.
66
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
(2) 16-bit instructions (( ): combination realized by using AX as rp) MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP, ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW
2nd Operand # word AX rp rp' 1st Operand AX (MOVM) ADDW
Note 1
saddrp saddrp
sfrp
!addr16 !!addr24
mem [saddrp] [%saddrg]
[WHL+]
byte
n
None
Note 2
(MOVW) (XCHW)
(MOVW) (XCHW)
(MOVW)Note 3 MOVW (XCHW)Note 3 (XCHW)
(MOVW) XCHW
MOVW XCHW
(MOVW) (XCHW) MULWNote 4 INCW DECW INCW DECW
(ADDW)Note 1 (ADDW)Note 1 (ADDW)Notes 1,3 (ADDW)Note 1 rp MOVW ADDW
Note 1
(MOVW) (XCHW)
MOVW XCHW
MOVW XCHW
MOVW XCHW
MOVW
SHRW SHLW
(ADDW)Note 1 ADDWNote 1 ADDWNote 1 ADDWNote 1 saddrp MOVW ADDW
Note 1
(MOVW)Note 3 MOVW
MOVW ADDWNote 1
(ADDW)Note 1 ADDWNote 1 XCHW
sfrp
MOVW
MOVW
MOVW
PUSH POP MOVTBLW
ADDWNote 1 (ADDW)Note 1 ADDWNote 1 !addr16 !!addr24 mem [saddrp] [%saddrg] PSW MOVW MOVW (MOVW) MOVW
PUSH POP
SP
ADDWG SUBWG
post
PUSH POP PUSHU POPU
[TDE+] byte
(MOVW)
SACW MACW MACSW
Notes 1. SUBW and CMPW are the same as ADDW. 2. Either the second operand is not used, or the second operation is not an operand address. 3. If saddr2 instead of saddr is used in this combination, the code length of some instructions is short. 4. MULUW and DIVUX are the same as MULW.
Data Sheet U12255EJ2V0DS00
67
PD784927, 784928, 784927Y, 784928Y
(3) 24-bit instructions (( ): combination realized by using WHL as rg) MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP
2nd Operand # imm24 WHL rg rg' 1st Operand WHL (MOVG) (ADDG) (SUBG) rg MOVG ADDG SUBG (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) (MOVG) (ADDG) (SUBG) MOVG ADDG SUBG (MOVG) ADDG SUBG MOVG MOVG INCG DECG PUSH POP saddrg !!addr24 mem1 [%saddrg] SP MOVG (MOVG) (MOVG) MOVG MOVG MOVG INCG DECG MOVG MOVG (MOVG) MOVG MOVG MOVG saddrg !!addr24 mem1 [%saddrg] SP NoneNote
Note
Either the second operand is not used, or the second operation is not an operand address.
(4) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET
2nd Operand CY saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit iaddr16.bit !addr24.bit MOV1 AND1 OR1 XOR1 MOV1 /saddr.bit /sfr.bit /A.bit /X.bit /PSWL.bit /PSWH.bit /mem2.bit /!addr16.bit /!!addr24.bit AND1 OR1 NoneNote
1st Operand CY
NOT1 SET1 CLR1
saddr.bit sfr.bit A.bit X.bit PSWL.bit PSWH.bit mem2.bit !addr16.bit !!addr24.bit
NOT1 SET1 CLR1 BF BT BTCLR BFSET
Note
Either the second operand is not used, or the second operation is not an operand address.
68
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
(5) Call/return and branch instructions CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL, BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Operand of instruction address Basic instruction BCNote BR CALL BR CALL BR RETCS RETCSB Compound instruction BF BT BTCLR BFSET DBNZ CALL BR CALL BR CALL BR CALL BR CALL BR CALLF CALLT BRKCS BRK RET RETI RETB $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] RBn None
Note
BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH are the same as BC.
(6) Other instructions ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
Data Sheet U12255EJ2V0DS00
69
PD784927, 784928, 784927Y, 784928Y
6. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage Symbol VDD AVDD1 AVDD2 AVSS1 AVSS2 Input voltage Analog input voltage (ANI0-ANI11) Output voltage Low-level output current VO IOL Pin 1 Total of all pins High-level output current IOH Pin 1 Total of all pins Operating ambient temperature Storage temperature TA Tstg VI VIAN VDD AVDD2 VDD < AVDD2 Conditions | VDD - AVDD1 | 0.5 V | VDD - AVDD2 | 0.5 V | AVDD1 - AVDD2 | 0.5 V Ratings -0.5 to +7.0 -0.5 to +7.0 -0.5 to +7.0 -0.5 to +0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 -0.5 to AVDD2 + 0.5 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 15 100 -10 -50 -10 to +70 -65 to +150 Unit V V V V V V V V V mA mA mA mA C C
Caution
If the rated value of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings therefore specify the values exceeding which the product may be physically damaged. Never exceed these values when using the product.
Operating Conditions
Clock Frequency 4 MHz fXX 16 MHz 32 kHz fXT 35 kHz Operating Ambient Temperature (TA) -10 to +70C Operating Conditions All functions CPU function only Subclock operation (CPU, watch, and port functions only) Supply Voltage (VDD) +4.5 to +5.5 V +4.0 to +5.5 V +2.7 to +5.5 V
70
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Oscillator Characteristics (main clock) (TA = -10 to +70C, VDD = AVDD = 4.0 to 5.5 V, VSS = AVSS = 0 V)
Resonator Crystal resonator
X1 X2 VSS
Recommended Circuit
Parameter Oscillation frequency (fXX)
MIN. 4
MAX. 16
Unit MHz
C1
C2
Oscillator Characteristics (subclock) (TA = -10 to +70C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
Resonator Crystal resonator
XT1 XT2 VSS
Recommended Circuit
Parameter Oscillation frequency (fXT)
MIN. 32
MAX. 35
Unit kHz
C1
C2
Caution
When using the main system clock and subsystem clock oscillator, wire the portion enclosed by the broken line in the above figures as follows to avoid the adverse influence of wiring capacitance: * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. Do not route the wiring in the neighborhood of a signal line through which a high alternating current flows. * Always keep the ground point of the capacitor of the oscillator to the same potential as VSS. Do not ground the capacitor to a ground pattern to which a high current flows. * Do not extract signals from the oscillation circuit. Exercise particular care in using the subsystem clock oscillator because the amplification factor of this circuit is kept low to reduce the current consumption.
Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U12255EJ2V0DS00
71
PD784927, 784928, 784927Y, 784928Y
DC Characteristics (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Low-level input voltage Symbol VIL1 VIL2 VIL3 High-level input voltage VIH1 VIH2 VIH3 Low-level output voltage VOL1 VOL2 VOL3 VOL4 High-level output voltage VOH1 VOH2 Input leakage current Output leakage current VDD supply current ILI ILO IDD1 Conditions Pins other than those listed in Note 1 below Pins listed in Note 1 below X1, X2 Pins other than those listed in Note 1 below Pins listed in Note 1 below X1, X2 IOL = 8.0 mA (pins in Note 2) IOL = 5.0 mA (pins in Note 4) IOL = 2.0 mA IOL = 100 A IOH = -1.0 mA IOH = -100 A 0 VI VDD 0 VO VDD Operation mode fXX = 16 MHz fXX = 8 MHz (low-frequency oscillation mode) Internally, 8 MHz main clock operation fXT = 32.768 kHz Subclock operation (CPU, watch, port) VDD = 2.7 V IDD2 HALT mode fXX = 16 MHz fXX = 8 MHz (low-frequency oscillation mode) Internally, 8 MHz main clock operation fXT = 32.768 MHz Subclock operation (CPU, watch, port) VDD = 2.7 V Data hold voltage Data hold current
Note 3
MIN. 0 0 0 0.7 VDD 0.8 VDD VDD - 0.5
TYP.
MAX. 0.3 VDD 0.2 VDD 0.4 VDD VDD VDD 1.0 0.6 0.45 0.25
Unit V V V V V V V V V V V V
VDD - 1.0 VDD - 0.4 10 10 30 50
A A
mA
50
80
A
10
25
mA
25
50
A
VDDDR IDDDR
STOP mode STOP mode Subclock oscillates VDDDR = 5.0 V STOP mode Subclock oscillates VDDDR = 2.7 V STOP mode Subclock stops VDDDR = 2.5 V
2.5 18 50
V
A A A
k
2.5
10
0.2
7.0
Pull-up resistor
RL
VI = 0 V
25
55
110
Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0 to P95/KEY4 2. P40 to P47 3. In the STOP mode in which the subclock oscillation is stopped, disconnect the feedback resistor, and connect the XT1 pin to VDD. 4. P46, P47
72
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
AC Characteristics CPU and peripheral circuit operation clock (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter CPU operation clock cycle time Symbol tCLK fXX = 16 MHz Conditions VDD = AVDD = 4.0 to 5.5 V CPU function only fXX = 16 MHz fXX = 8 MHz low-frequency oscillation mode (Bit 7 of CC = 1) Peripheral operation clock cycle time tCLK1 fXX = 16 MHz fXX = 8MHz low-frequency oscillation mode (Bit 7 of CC = 1) 125 ns TYP. 125 Unit ns
Serial interface (1) SIOn: n = 1 or 2 (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Serial clock cycle time Symbol tCYSK Input Output Conditions External clock fCLK1/8 fCLK1/16 fCLK1/32 fCLK1/64 fCLK1/128 fCLK1/256 Serial clock high- and low-level widths SIn setup time (vs. SCKn ) SIn hold time (vs. SCKn ) SOn output delay time (vs. SCKn ) tWSKH tWSKL tSSSK tHSSK tDSSK Input Output External clock Internal clock MIN. 1.0 1.0 2.0 4.0 8.0 16 32 420 tCYSK/2 - 50 100 400 0 300 MAX. Unit
s s s s s s s
ns ns ns ns ns
Remarks 1. fCLK1: operating clock of peripheral circuit (8 MHz) 2. n = 1 or 2 (2) SIO2 only (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter SCK2(8) STRB Strobe high-level width BUSY setup time (vs. BUSY detection timing) BUSY hold time (vs. BUSY detection timing) BUSY inactive SCK2(1) tLBUSY tCYSK + tWSKH tHBUSY 100 ns Symbol tDSTRB tWSTRB tSBUSY Conditions MIN. tWSKH tCYSK - 30 100 MAX. tCYSK tCYSK + 30 ns ns Unit
Remarks 1. The value in ( ) following SCK2 indicates the number of SCK2. 2. BUSY is detected after the time of (n + 2) x tCYSK (n = 0, 1, and so on) in respect to SCK2 (8) . 3. BUSY inactive SCK2 (1) is the value when data has been completely written to SIO2.
Data Sheet U12255EJ2V0DS00
73
PD784927, 784928, 784927Y, 784928Y
I2C bus mode (PD784928Y subseries only)
Parameter Symbol Standard Mode MIN. SCL clock frequency Bus free time (between stop and start conditions) Hold time Note 1 SCL clock low-level width SCL clock high-level width Start/restart condition setup time Data hold time CBUS compatible master I2 C bus tSU : DAT tR tF tSU : STO tSP tHD : STA tLOW tHIGH tSU : STA tHD : DAT 4.0 4.7 4.0 4.7 5.0 0Note 2 250 - - 4.0 - - - - - - - - 1000 300 - - 0.6 1.3 0.6 0.6 - 0Note 2 100Note 4 20+0.1CbNote 5 20+0.1CbNote 5 0.6 0 - - - - - 0.9Note 2 - 300 300 - 50 fCLK tBUF 0 4.7 MAX 100 - High-speed Mode MIN 0 1.3 MAX. 400 - kHz Unit
s s s s s s s
ns ns ns
Data setup time SDA and SCL signal rise time SDA and SCL signal fall time Stop condition setup time Pulse width of spike restrained by input filter Each bus line capacitative load
s
ns
Cb
-
400
-
400
pF
Notes 1. The first clock pulse is generated at the start condition after this period. 2. The device needs to internally supply a hold time of at least 300 ns for the SDA signal to fill the undefined area at the falling edge of the SCL (VIHmin. of the SCL signal). 3. Unless the device extends the low hold time (tLOW) of the SCL signal, it is necessary to fill only the maximum data hold time (tHD : the following conditions: * When the device does not extend the low hold time of the SCL signal tSU :
DAT DAT).
4. The high-speed mode I2C bus can be used in the standard mode I2C bus system. In this case, satisfy
250 ns
* When the device extends the low hold time of the SCL signal Send the next data bit to the SDA line before releasing the SCL line (tRmax. + tSU:DAT = 1000 + 250 = 1250 ns : in the standard mode I2C bus specification) 5. Cb: Total capacitance of one bus line (unit: pF)
74
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Other operations (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Timer input signal low-level width Symbol tWCTL Condition When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input Timer input signal high-level width tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input Timer input signal valid edge input cycle CSYNCIN low-level width tPERIN tWCR1L When DFGIN, CFGIN, or DPGIN is input When digital noise rejection circuit is not used When digital noise rejection circuit is used (Bit 4 of INTM2 = 0) When digital noise rejection circuit is used (Bit 4 of INTM2 = 1) CSYNCIN high-level width tWCR1H When digital noise rejection circuit is not used When digital noise rejection circuit is used (Bit 4 of INTM2 = 0) When digital noise rejection circuit is used (Bit 4 of INTM2 = 1) Digital noise rejection circuit Passed pulse width Rejected pulse width tWSEP Bit 4 of INTM2 = 0 Bit 4 of INTM2 = 1 Bit 4 of INTM2 = 0 Bit 4 of INTM2 = 1 NMI low-level width NMI high-level width INTP0, INTP3 low-level widths INTP0, INTP3 high-level widths INTP1, KEY0-KEY4 low-level widths tWNIL tWNIH tWIPL0 tWIPH0 tWIPL1 Mode other than STOP mode In STOP mode, for releasing STOP mode INTP1, KEY0-KEY4 high-level widths tWIPH1 Mode other than STOP mode In STOP mode, for releasing STOP mode INTP2 low-level width tWIPL2 In normal mode, with main clock Normal mode, with subclock Sampling = fCLK Sampling = fCLK/128 Sampling = fCLK Sampling = fCLK/128 VDD = AVDD = 2.7 to 5.5 V VDD = AVDD = 2.7 to 5.5 V 108tCLK1 180tCLK1 10 10 2tCLK1 2tCLK1 2tCLK1 10 2tCLK1 10 2tCLK1 32Note 61 7.9Note 10 2tCLK1 32Note 61 7.9Note 10 10 104tCLK1 176tCLK1 ns ns ns ns 180tCLK1 ns 8tCLK1 108tCLK1 ns ns 180tCLK1 ns 2 8tCLK1 108tCLK1 tCLK1 ns MIN. tCLK1 MAX. Unit ns
s
ns ns
s s
ns ns ns
s
ns
s
ns
s s
ms
In STOP mode, for releasing STOP mode INTP2 high-level width tWIPH2 In normal mode, with main clock Normal mode, with subclock Sampling = fCLK Sampling = fCLK/128 Sampling = fCLK Sampling = fCLK/128
s
ns
s s
ms
In STOP mode, for releasing STOP mode RESET low-level width tWRSL
s s
Note
If a high or low level is successively input two times during the sampling period, a high or low level is detected.
Remark tCKL1: operating clock cycle time of peripheral circuit (125 ns)
Data Sheet U12255EJ2V0DS00
75
PD784927, 784928, 784927Y, 784928Y
Clock output operation (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter CLO cycle time CLO low-level width CLO high-level width CLO rise time CLO fall time Symbol tCYCL tCLL tCLH tCLR tCLF nT tCYCL/2 25 tCYCL/2 25 Condition MIN. 125 37.5 37.5 MAX. 16000 8025 8025 25 25 Unit ns ns ns ns ns
Remarks 1. n: system clock division 2. T = 1/fCLK Data hold characteristics (TA = -10 to +70C, VDD = AVDD = 2.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Low-level input voltage High-level input voltage Symbol VIL VIH Condition Special pins (pins in Note) MIN. 0 0.9 VDDDR TYP. MAX. 0.1 VDDDR VDDDR Unit V V
Note
RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/ KEY4
Watch function (TA = -10 to +70C, VDD = AVDD = 2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter Subclock oscillation hold voltage Hardware watch function operating voltage Symbol VDDXT VDDW Condition MIN. 2.7 2.7 MAX. Unit V V
Subclock oscillation stop detection flag (TA = -10 to +70C, VDD = AVDD = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Oscillation stop detection width Symbol tOSCF Condition MIN. 45 MAX. Unit
s
A/D converter characteristics (TA = -10 to +70C, VDD = AVDD = AVREF = 4.5 to 5.5 V, VSS = AVSS = 0 V)
Parameter Resolution Total error Quantization error Conversion time tCONV Bit 4 of ADM = 0 Bit 4 of ADM = 1 Sampling time tSAMP Bit 4 of ADM = 0 Bit 4 of ADM = 1 Analog input voltage Analog input impedance AVREF current VIAN ZAN AIREF 160tCLK1 80tCLK1 32tCLK1 16tCLK1 0 1000 0.4 1.2 AVREF AVREF = VDD Symbol Condition MIN. 8 2.0 1/2 TYP. MAX. Unit bit % LSB
s s s s
V M mA
76
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
VREF amplifier (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Reference voltage Charge current Symbol VREF ICHG Sets AMPM0.0 to 1 (pins in Note) Condition MIN. 2.35 300 TYP. 2.50 MAX. 2.65 Unit V
A
Note
RECCTL+, RECCTL-, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN
CTL amplifier (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter CTL+, - input resistance Feedback resistance Bias resistance Minimum voltage gain Maximum voltage gain Gain selecting step Same phase signal elimination ratio Symbol RICTL RFCTL RBCTL GCTLMIN GCTLMAX SGAIN CMR DC, voltage gain: 20 dB Condition MIN. 2 20 20 17 71 TYP. 5 50 50 20 75 1.77 50 VREF + 0.47 VREF + 0.50 VREF + 0.53 VREF + 0.27 VREF + 0.30 VREF + 0.33 VREF - 0.53 VREF - 0.50 VREF - 0.47 VREF - 0.33 VREF - 0.30 VREF - 0.27 150 200 250 MAX. 10 100 100 22 Unit k k k dB dB dB dB V V V V mV V V V V
High comparator set voltage of waveform shaping VPBCTLHS High comparator reset voltage of waveform shaping VPBCTLHR Low comparator set voltage of waveform shaping VPBCTLLS
Low comparator reset voltage of waveform shaping VPBCTLLR Comparator Schmitt width of waveform shaping High comparator voltage of CTL flag S Low comparator voltage of CLT flag S High comparator voltage of CTL flag L Low comparator voltage of CTL flag L VPBSH VFSH VFSL VFLH VFLL
VREF + 1.00 VREF + 1.05 VREF + 1.10 VREF - 1.10 VREF - 1.05 VREF - 1.00 VREF + 1.40 VREF + 1.45 VREF + 1.50 VREF - 1.50 VREF - 1.45 VREF - 1.40
Data Sheet U12255EJ2V0DS00
77
PD784927, 784928, 784927Y, 784928Y
CFG amplifier (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Voltage gain 1 Voltage gain 2 CFGAMPO High-level output current CFGAMPO Low-level output current High comparator voltage Low comparator voltage Duty accuracy Symbol GCFG1 GCFG2 IOHCFG IOLCFG VCFGH VCFGL PDUTY Note Condition fi = 2 kHz, open loop fi = 30 kHz, open loop DC DC MIN. 50 34 -1 0.1 VREF + 0.09 VREF + 0.12 VREF + 0.15 VREF - 0.15 VREF - 0.12 VREF - 0.09 49.7 50.0 50.3 TYP. MAX. Unit dB dB mA mA V V %
Note
The conditions include the following circuit and input signal. Input signal : Sine wave input (5 mVp-p) fi = 1 kHz Voltage gain: 50 dB
1 k -+ 22 F 330 k CFGIN
PD784927
CFGAMPO 0.01 F
CFGCPIN
DFG amplifier (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Voltage gain Feedback resistance Input protection resistance High comparator voltage Low comparator voltage Symbol GDFG RFDFG RIDFG VDFGH VDFGL Condition fi = 900 Hz, open loop MIN. 50 160 400 150 VREF + 0.07 VREF + 0.10 VREF + 0.14 VREF - 0.14 VREF - 0.10 VREF - 0.07 640 TYP. MAX. Unit dB k V V
Caution
Set the input resistance connected to the DFGIN pin to 16 k or below. Connecting a resistor exceeding that value may cause the DFG amp to oscillate.
78
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
DPG amplifier (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Voltage gain High comparator voltage Symbol GDPG VDPGH1 VDPGH2 VDPGH3 Low comparator voltage VDPGL1 VDPGL2 VDPGL3 fI = 30 Hz Condition MIN. TYP. 20 MAX. Unit dB V V V V V V
SELDPGHL0 = 0, SELDPGHL1 = 0 VREF + 0.02 VREF + 0.05 VREF + 0.08 SELDPGHL0 = 1, SELDPGHL1 = 0 VREF + 0.56 VREF + 0.60 VREF + 0.64 SELDPGHL0 = 0, SELDPGHL1 = 1 VREF - 0.44 VREF - 0.40 VREF - 0.36 SELDPGHL0 = 0, SELDPGHL1 = 0 VREF - 0.08 VREF - 0.05 VREF - 0.02 SELDPGHL0 = 1, SELDPGHL1 = 0 VREF + 0.36 VREF + 0.40 VREF + 0.44 SELDPGHL0 = 0, SELDPGHL1 = 1 VREF - 0.64 VREF - 0.60 VREF - 0.56
Caution
When both the SELDPGHL0 and SELDPGHL1 are set to 0, the DPG amplifier is not used. Therefore, be sure to set AMPC.7 (ENDPG) to 0.
Ternary separation circuit (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance High comparator voltage Low comparator voltage Symbol ZIPFG VPFGH VPFGL Condition MIN. 20 TYP. 50 MAX. 100 VREF + 0.9 VREF - 1.0 Unit k V V
VREF + 0.5 VREF + 0.7 VREF - 1.4 VREF - 1.2
CSYNC comparator (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance High comparator voltage Low comparator voltage Symbol ZICSYN VCSYNH VCSYNL Condition MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF + 0.07 VREF + 0.10 VREF + 0.13 VREF - 0.13 VREF - 0.10 VREF - 0.07
Reel FG comparator (AC coupling) (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter Input impedance High comparator voltage Low comparator voltage Symbol ZIRLFG VRLFGH VRLFGL Condition MIN. 20 TYP. 50 MAX. 100 Unit k V V
VREF + 0.02 VREF + 0.05 VREF + 0.08 VREF - 0.08 VREF - 0.05 VREF - 0.02
RECCTL driver (TA = 25C, VDD = AVDD = 5 V, VSS = AVSS = 0 V)
Parameter RECCTL+, - high-level output voltage RECCTL+, - low-level output voltage CTLDLY internal resistance CTLDLY charge current CTLDLY discharge current Symbol VCHREC VOLREC RCTL IOHCTL IOLCTL Use of internal resistor Condition IOH = -4 mA IOL = 4 mA 40 -3 -3 70 MIN. VDD - 0.8 0.8 140 TYP. MAX. Unit V V k mA mA
Data Sheet U12255EJ2V0DS00
79
PD784927, 784928, 784927Y, 784928Y
Timing waveform AC timing test point
0.8 VDD or 2.2 V Test point 0.8 V
0.8 VDD or 2.2 V 0.8 V
Serial transfer timing (SIOn: n = 1 or 2)
tWSKL SCKn tCYSK
tWSKH
tSSSK
tHSSK
SIn
Input data
tDSSK SOn Output data
80
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Serial transfer timing (SIO2 only) No busy processing
tWSKL SCK2 7 tCYSK BUSY Active high tDSTRB STRB Busy invalid tWSTRB tWSKH 8 9 10 1 2
Continuation of busy processing
tWSKL SCK2 7 tCYSK BUSY tWSKH 8 9 tSBUSY 10 10+n tSBUSY
Active high tDSTRB tWSTRB
STRB
End of busy processing
tWSKL SCK2 7
tWSKH 8 tCYSK 9 10+n tHBUSY 11+n tLBUSY 1
BUSY
Active high
Caution
When an external clock is selected as the serial clock, do not use the busy control or strobe control.
Data Sheet U12255EJ2V0DS00
81
PD784927, 784928, 784927Y, 784928Y
I2C bus mode (PD784928Y subseries only)
tLOW SCL tHD : DAT tHD : STA tHIGH tSU : DAT tF tSU : STA tHD : STA tSP tSU : STO tR
SDA tBUF Stop condition Start condition Restart condition Stop condition
82
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Super timer unit input timing
tWCTH When DFGIN, CFGIN, DPGIN, REEL0IN, or REEL1IN logic level is input 0.8 VDD 0.8 V
tWCTL
tWCR1H When CSYNCIN logic level is input 0.8 VDD 0.8 V
tWCR1L
Interrupt request input timing
tWNIH NMI 0.8 VDD 0.8 V
tWNIL
tWIPH0 INTP0, INTP3 0.8 VDD 0.8 V
tWIPL0
tWIPH1 0.8 VDD 0.8 V
tWIPL1
INTP1, KEY0-KEY4
tWIPH2 0.8 VDD INTP2 0.8 V
tWIPL2
Data Sheet U12255EJ2V0DS00
83
PD784927, 784928, 784927Y, 784928Y
Reset input timing
tWRSL
RESET 0.8 V
Clock output timing
tCLH CLO 0.8 VDD 0.8 V tCLR tCLF tCLL tCYCL
84
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
7. PACKAGE DRAWING
100 PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end
CD
S Q R
100 1
26 25
F G P H I
M
J K M
N
NOTE Each lead centerline is located within 0.08 mm (0.003 inch) of its true position (T.P.) at maximum material condition.
L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 16.000.20 14.000.20 14.000.20 16.000.20 1.00 1.00 0.22 +0.05 -0.04 0.08 0.50 (T.P.) 1.000.20 0.500.20 0.17 +0.03 -0.07 0.08 1.400.05 0.100.05 3 +7 -3 1.60 MAX. INCHES 0.6300.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.6300.008 0.039 0.039 0.0090.002 0.003 0.020 (T.P.) 0.039 +0.009 -0.008 0.020 +0.008 -0.009 0.007 +0.001 -0.003 0.003 0.0550.002 0.0040.002 3 +7 -3 0.063 MAX. S100GC-50-8EU
Remark The package dimensions and materials of ES versions are the same as those of mass-production versions.
Data Sheet U12255EJ2V0DS00
85
PD784927, 784928, 784927Y, 784928Y
100PIN PLASTIC QFP (14x20)
A B
80 81
51 50
detail of lead end CD
S Q R
100 1
31 30
F G H I
M
J
P
K M N L
ITEM A B C D F G H I J K L M N P Q R S MILLIMETERS 23.60.4 20.00.2 14.00.2 17.60.4 0.8 0.6 0.300.10 0.15 0.65 (T.P.) 1.80.2 0.80.2 0.15 +0.10 -0.05 0.10 2.70.1 0.10.1 55 3.0 MAX. INCHES 0.9290.016 0.795 +0.009 -0.008 0.551 +0.009 -0.008 0.6930.016 0.031 0.024 0.012 +0.004 -0.005 0.006 0.026 (T.P.) 0.071 +0.008 -0.009 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 +0.005 -0.004 0.0040.004 55 0.119 MAX. P100GF-65-3BA1-3
NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition.
Remark The package dimensions and materials of ES versions are the same as those of mass-production versions.
86
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
8. RECOMMENDED SOLDERING CONDITIONS
Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Caution PD784927GC-xxx-8EU, 784927YGC-xxx-8EU, 784928GC-xxx-8EU, and 784928YGC-xxx-8EU are under development. Therefore their soldering conditions are not defined. Table 8-1. Surface Mount Type Soldering Conditions
PD784927GF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD784928GF-xxx-3BA : 100-pin plastic QFP (14 x 20 mm) PD784927YGF-xxx-3BA: 100-pin plastic QFP (14 x 20 mm) PD784928YGF-xxx-3BA: 100-pin plastic QFP (14 x 20 mm)
Soldering Method Soldering Conditions Recommended Conditions Symbol IR35-00-3
Infrared reflow
Package peak temperature: 235C, Time: 30 secs. max. (210C min.), Number of times: three times max. Package peak temperature: 215C, Time: 40 secs. max. (200C min.), Number of times: three times max.
VPS
VP15-00-3
Wave soldering
Solder bath temperature: 260C max., Time: 10 secs. max., Number of times: once, Preheating temperature: 120C max.(Package surface temperature) Pin temperature: 300C max., Time: three secs. max. (per device side)
WS60-00-1
Partial heating
--
Caution Do not use two or more soldering methods in combination (except partial heating).
Data Sheet U12255EJ2V0DS00
87
PD784927, 784928, 784927Y, 784928Y
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for developing systems using the PD784927. Refer to (5) Cautions when the development tools are used. (1) Language processing software
RA78K4 CC78K4 DF784928 CC78K4-L 78K/IV series common assembler package 78K/IV series common C compiler package Device file for the PD784928, 784928Y subseries 78K/IV series common C compiler library source file
(2) Flash memory writing tools
Flashpro II, III (Part number: FL-PR2, FL-PR3, PG-FPIII) FA-100GC FA-100GF Dedicated flash programmer
Adapter for writing 100-pin plastic LQFP (GC-8EU type) flash memory. Be sure to connect depending on the target product. Adapter for writing 100-pin plastic QFP (GF-3BA type) flash memory. Be sure to connect depending on the target product.
(3) Debugging tools * When using the IE-78K4-NS in-circuit emulator
IE-78K4-NS IE-70000-MC-PS-B IE-70000-98-IF-C IE-70000-CD-IF-A IE-70000-PC-IF-C IE-784928-NS-EM1 EP-784915-GF-R EV-9200GF-100 NQPACK100RB ID78K4-NS SM78K4 DF784928 78K/IV series common in-circuit emulator Power supply unit for IE-78K4-NS Interface adapter necessary when a PC-9800 series computer (except notebook personal computer) is used as host machine (C bus compatible) PC card and interface cable necessary when a notebook personal computer is used as host machine (PCMCIA socket compatible) Interface adapter necessary when an IBM PC/ATTM compatible machine is used as host machine (ISA bus compatible) Emulation board for emulating the PD784928, 784928Y subseries Emulation probe for PD784915 subseries common 100-pin plastic QFP (GC-3BA type) and 100-pin plastic LQFP (GC-8EU type). Conversion socket to be mounted on the board of the target system for 100-pin plastic QFP (GF-3BA type). It is used in LCC system. Conversion socket to be mounted on the board of the target system for 100-pin plastic QFP (GF-3BA type). It is used in QFP system. Integrated debugger for IE-78K4-NS 78K/IV series common system simulator Device file for the PD784928, 784928Y subseries
88
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
* When using the IE-784000-R in-circuit emulator
IE-784000-R IE-70000-98-IF-C IE-70000-PC-IF-C IE-78000-R-SV3 IE-784928-NS-EM1 IE-784915-R-EM1 IE-784000-R-EM IE-78K4-R-EX3 EP-784915-GF-R EV-9200GF-100 NQPACK100RB ID78K4 SM78K4 DF784928 78K/IV series common in-circuit emulator Interface adapter necessary when a PC-9800 series computer (except notebook personal computer) is used as host machine (C bus compatible) Interface adapter necessary when an IBM PC/AT compatible machine is used as host machine (ISA bus compatible) Interface adapter and cable necessary when an EWS is used as host machine Emulation board for emulating the PD784928, 784928Y subseries and PD784915 subseries 78K/IV series common emulation board Conversion board for 100-pin products necessary when the IE-784928-NS-EM1 is used in the IE-784000-R. Not necessary when the IE-784915-R-EM1 is used. Emulation probe for PD784915 subseries common 100-pin plastic QFP (GC-3BA type) and 100-pin plastic LQFP (GC-8EU type). Conversion socket to be mounted on the board of the target system for 100-pin plastic QFP (GF-3BA type). It is used in LCC system. Conversion socket to be mounted on the board of the target system for 100-pin plastic QFP (GF-3BA type). It is used in QFP system. Integrated debugger for IE-784000-R 78K/IV series common system simulator Device file for the PD784928, 784928Y subseries
(4) Real-time OS
RX78K/IV MX78K4 Real-time OS for 78K/IV series OS for 78K/IV series
Data Sheet U12255EJ2V0DS00
89
PD784927, 784928, 784927Y, 784928Y
(5) Cautions when the development tools are used * The ID78K4-NS, ID78K4, and SM78K4 are used in combination with the DF784928. * The CC78K4 and RX78K/IV are used in combination with the RA78K4 and DF784928. * FL-PR2, FL-PR3, FA-100GC, and FA-100GF are products of Naito Densei Machida Mfg. Co., Ltd. (TEL: 044822-3813). Contact an NEC distributor when purchasing these products. * NQPACK100RB is a product of Tokyo Eletech Corp. Reference: Daimaru Kogyo, Ltd. Electronics Dept. (TEL: Tokyo 03-3820-7112) Electronics 2nd Dept. (TEL: Osaka 06-6244-6672) * Host machines and OSs compatible with the software are as follows:
Host Machine [OS]
PC PC-9800 Series IBM PC/AT compatible machines [Japanese/English Windows]
Note Note
EWS HP9000 series 700 TM [HP-UX TM ] SPARCstation TM [SunOS TM , Solaris TM ] NEWSTM (RISC) [NEWS-OS TM]
[Windows TM ]
Software RA78K4 CC78K4 ID78K4-NS ID78K4 SM78K4 RX78K/IV MX78K4
-
-
Note Note
Note
DOS based software
90
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
APPENDIX B. RELATED DOCUMENTS
Device-related documents
Document Japanese Document No. English U12648E This document - U12188E - U12271E U11361E U10905E - - U10095E
PD784928, 784928Y Subseries User's Manual - Hardware PD784927, 784928, 784927Y, 784928Y Data Sheet PD784928 Subseries Special Function Register Table PD78F4928 Preliminary Product Information PD784928Y Subseries Special Function Register Table PD78F4928Y Preliminary Product Information
PD784915, 784928, 784928Y Subseries Application Note - VCR Servo
78K/IV Series User's Manual - Instruction 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note - Software Basics
U12648J U12255J U12798J U12188J U12719J U12271J U11361J U10905J U10594J U10595J U10095J
Development tool-related documents (User's Manuals)
Document Japanese RA78K4 Assembler Package Operation Language RA78K4 Structured Assembler Preprocessor CC78K4 C Compiler Operation Language IE-78K4-NS IE-784000-R IE-784928-NS-EM1 IE-784915-R-EM1, EP-784915GF-R SM78K4 System Simulator Windows Based SM78K Series System Simulator ID78K4-NS Integrated Debugger ID78K4 Integrated Debugger Windows Based ID78K4 Integrated Debugger HP-UX, SunOS, NEWS-OS Based Reference U11334J U11162J U11743J U11572J U11571J U13356J U12903J U13819J U10931J U10093J Document No. English U11334E U11162E U11743E U11572E U11571E U13356E EEU-1534 U13819E U10931E U10093E U10092E U12796E U10440E U11960E
External Part User Open U10092J Interface Specifications Reference Reference Reference U12796J U10440J U11960J
Caution
The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system.
Data Sheet U12255EJ2V0DS00
91
PD784927, 784928, 784927Y, 784928Y
Embedded software-related documents (User's Manual)
Document Japanese 78K/IV Series Real-Time OS Fundamental Installation Debugger 78K/IV Series OS, MX78K4 Fundamental U10603J U10604J U10364J U11779J Document No. English U10603E U10604E - -
Other documents
Document Japanese SEMICONDUCTORS SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Guide to Microcomputer-Related Products by Third Party X13769X C10535J C11531J C10983J C11892J U11416J C10535E C11531E C10983E C11892E - Document No. English
Caution
The contents of the above related documents are subject to change without notice. Be sure to use the latest edition of the document when designing your system.
92
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
[MEMO]
Data Sheet U12255EJ2V0DS00
93
PD784927, 784928, 784927Y, 784928Y
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I 2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
EEPROM and FIP are trademarks of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 Series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEW-OS are trademarks of Sony Corporation.
94
Data Sheet U12255EJ2V0DS00
PD784927, 784928, 784927Y, 784928Y
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: * Device availability * Ordering information * Product release schedule * Availability of related technical literature * Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) * Network requirements In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 58 00 Fax: 01-30-67 58 99 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Spain Office Madrid, Spain Tel: 91-504-2787 Fax: 91-504-2860
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 65-253-8311 Fax: 65-250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Rodovia Presidente Dutra, Km 214 07210-902-Guarulhos-SP Brasil Tel: 55-11-6465-6810 Fax: 55-11-6465-6829
J99.1
Data Sheet U12255EJ2V0DS00
95
PD784927, 784928, 784927Y, 784928Y
The documents referred to in this publication may include preliminary versions. However, preliminary versions are not marked as such.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98.8

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